verilog

Type of issue: feature request

I'm not sure about if it was a system configuration problem on my computer. Most of my computers runs Archlinux with Java 18. It seems the pin text of RAM is too large and overlaps each other:

While I didn't found a way to configure font of the canvas in menus. I found that a modifica

Thanks for taking the time to report this.

What would you like added/supported?

// File: dly_warning.sv

// verilator lint_off ASSIGNDLY

module dly_warning (
    input logic a_in,
    input logic [2:0] delaycw,

    output logic a_out
);

timeunit 1ns;
timeprecision 1ns;

time dly;

assign dly = 5 * delaycw;
assign #dly a_out = a_in;     // Warning ASS

#23 was closed, and a follow on action was to document how to configure the cocotb logger to separate it and the simulator stdout.

Tuo Xie requested the ability to visualize clocking (pins & wires I believe). We should make it easier to visualize subsets of the device routing resource and types of routing nets.

Proposed Behaviour

Add filtering to the rr_nodes displayed (ToggleRR), and to the nets displayed (ToggleNets). I think we should have an option to filter what is shown by node type, node name (segment or pin t