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soft-core

Here are 14 public repositories matching this topic...

ZipCPU / zipcpu

A small, light weight, RISC CPU soft core

cpu fpga verilog cross-compiler wishbone soft-core verilator zipcpu wishbone-bus risc-cpu

Updated May 6, 2022
Verilog

neorv32

stnolting / neorv32

🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

microcontroller embedded cpu fpga core processor vhdl gdb riscv safety rtos soc risc-v openocd soft-core system-on-chip rv32

Updated May 21, 2022
VHDL

stnolting / neo430

💻 A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

open-source microcontroller fpga processor vhdl gcc customizable msp430 soc soft-core system-on-chip msp430-gcc

Updated Nov 23, 2021
VHDL

sy2002 / QNICE-FPGA

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

c tutorial cpu fpga vhdl assembler open-hardware fpga-game sd-card vga 16-bit soft-core system-on-chip vhdl-examples qnice learn-fpga fpga-tutorial vhdl-tutorial

Updated Nov 27, 2021
Assembly

lxp32 / lxp32-cpu

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

cpu fpga x86-64 vhdl riscv x86 risc risc-v wishbone soft-core risc-processor wishbone-bus risc-cpu

Updated Oct 21, 2021
Assembly

WangXuan95 / FPGA-DDR-SDRAM

DDR1 controller to realize mass, cheap memory for FPGAs.

fpga controller rtl verilog systemverilog soft-core axi4 ddr-sdram ddr1

Updated Apr 17, 2022
SystemVerilog

mrisc32 / mrisc32-a1

A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA

cpu vhdl risc soft-core fpu mrisc32

Updated May 1, 2022
VHDL

matt-alencar / fpga-uart-tx-rx

Basic UART TX/RX module for FPGA

fpga verilog uart hdl uart-protocol soft-core uart-interface

Updated Oct 18, 2018
Verilog

wyvernSemi / riscV

Open source ISS and logic RISC-V 32 bit project

linux c-plus-plus fpga processor iss embedded-systems verilog cpu-model risc-v soft-core 32-bit risc-processor co-simulation

Updated Apr 22, 2022
C++

wyvernSemi / mico32

LatticeMico32 instruction set simulator project

linux c-plus-plus embedded fpga processor gdb iss python3 tcp-socket debug tkinter risc cpu-model 32-bits soft-core serial-communication latticemico32 com0com

Updated Nov 30, 2021
C++

true-grue / uzh

Uzh compiler

python embedded fpga compiler stack-based soft-core

Updated Oct 21, 2018
Python

riscv-atom

saursin / riscv-atom

Open

Redundancy in makefile

saursin commented Dec 30, 2021

There is a redundancy in the makefile while declaring Verilog files for the targets - atombones and hydrogensoc. Clearly these targets have some files that are needed by both and some files that only one of the targets requires.

Read more

good first issue

Open

Add more SCAR tests

semahawk / icarium

Trying to implement a soft core SoC

verilog verilog-hdl wishbone soft-core system-on-chip softcore wishbone-bus

Updated Apr 6, 2019
Verilog

RainingComputers / SRP16

SRP16 is free and open ISA for 16-bit CPUs and Microcontrollers.

cpu microcontrollers verilog isa risc instruction-set-architecture soft-core open-embedded open-isa isa-specification

Updated Oct 17, 2021
C++

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