OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

Python implementation of the exact Riemann solver of Toro (1999).

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

my UVM training projects

Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols that are widely used in today's complex systems.The I2C bus has a minimum pin count requirement and therefore a smaller footprint on the board. The SPI bus provides a synchronized serial link with performance in MHz range.The project implements the bridge between the two protocols and serves as an interface between these two which allow direct communication and a solution to reduce development time and cost for complex embedded systems.

Basics of UVM via an APB slave

An inference engine for Leon (https://github.com/epfl-lara/leon) that verifies resource bounds of functional Scala programs

Verification, Validation, Uncertainty Quantification and Qualification Project

Example which helps understand modelling of a simple SV TB. For UVM implementation refer the repository "fifo_tb_uvm".

ATM-Utopia module and testbench.

Program i cili mundeson regjistrimin, kerkimin dhe fshirjen e adresave duke u bazuar longitude dhe latitude. Permban: 1. SQL, siguri ndaj SQL-Injection 2. Siguri te te dhenave - SaltHash 3. Dy mode operimi admin & user 4.Mailing dhe 5.MultiLanguage

This repo contains golden vector and randomization testbenches for SRAM module.