lowRISC / opentitan
OpenTitan: Open source silicon root of trust
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| 2021 | 2022 | 2023 |

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OpenTitan: Open source silicon root of trust
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
SystemVerilog modules and classes commonly used for verification
open-source Ethenet media access controller for Ariane on Genesys-2
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
SweRV EL2 Core
Generic Register Interface (contains various adatpers)
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
APB Timer Unit
AXI X-Bar
IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs