verification

• Missing information on how to create other databases
• Missing information on how to switch to other databases
• When using time travel, we don’t know where to get the transaction number from - we should show this to the user after committing data (this may be a missing capability in immudb / tools).
• The last long query example in the quick start is incorrect (incorrect

The test suite is currently split between two organization models: some tests are organized by the component, or the feature, they test (like this), and a lot of tests are organized by the number of the GitHub issue they verify (like [this](https://github.com/mockk/mockk/blob/master/mockk/jvm/s

A formula like forall x1. forall. x2. exists x3. phi gets resugared to, and hence pretty printed as, forall x1 x2 x3. phi. The bug is in the uncurry function in FStar.Syntax.Reguar.fs.

#23 was closed, and a follow on action was to document how to configure the cocotb logger to separate it and the simulator stdout.

Various hacks are documented in stitch with comments marked with XXX.
Some of them are no longer necessary and can be removed, others are still needed and could be improved by having them link a relevant issue or by describing the error they avoid in some more detail.

This issue is to make a pass over the stitch-lh code to update them. Fixing them in the LH repo would suffice for now (stitch-l

Currently, this is indicated using colour only, which is unhelpful if you are red/green colourblind.

The vergen crate seems a better alternative than manually calling git

https://github.com/viperproject/prusti-dev/blob/69325d35ec51a45118ec93ed4e46957e1d08f903/prusti/build.rs#L12-L16
https://github.com/viperproject/prusti-dev/blob/69325d35ec51a45118ec93ed4e46957e1d08f903/prusti/build.rs#L21-L25

Here is the problem:

$ make compile
Traceback (most recent call last):
File "C:\My_Designs\probe_fpga_design_1\run.py", line 336, in
main()
File "C:\My_Designs\probe_fpga_design_1\run.py", line 181, in main
vu.add_osvvm()
File "c:\my_designs\probe_fpga_design_1\deps\vunit\vunit\ui_init_.py", line 1030, in add_osvvm
self.builtins.add("osvvm")
File "c:\my