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Andrew Waterman aswaterman

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@sifive @riscv @ucb-bar
Berkeley, CA, USA

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Popular repositories

trainwreck Public

Original RISC-V 1.0 implementation. Not supported.

Verilog 24 12
rocket-chip Public

Forked from chipsalliance/rocket-chip

Rocket Chip Generator

Scala

1,284 contributions in the last year

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Contribution activity

April 2022

Created 17 commits in 7 repositories

Opened 3 pull requests in 3 repositories

riscv/riscv-v-spec 1 merged

v[f]slide1down respects the mask policy Apr 15

riscv-non-isa/riscv-elf-psabi-doc 1 merged

Minor grammar and style improvements Apr 13

riscv-software-src/riscv-isa-sim 1 merged

Rename processor_t::set_csr to put_csr to fix build on RISC-V Apr 7

Reviewed 12 pull requests in 5 repositories

riscv-software-src/riscv-isa-sim 7 pull requests

chipsalliance/chisel3 2 pull requests

Enable Clock Invalidation Apr 15
Micro-optimize String building in _computeName Apr 5

riscv-non-isa/riscv-toolchain-conventions 1 pull request

Conventions for vendor extension Apr 23

chipsalliance/rocket-chip 1 pull request

Support building PTW with no PTECache Apr 12

riscv-non-isa/riscv-asm-manual 1 pull request

Expand description of registers and their uses Apr 1

43 contributions in private repositories Apr 4 – Apr 23