The Wayback Machine - https://web.archive.org/web/20220324220512/https://github.com/topics/rtl

#

rtl

Here are 559 public repositories matching this topic...

youngsoft / MyLinearLayout

MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use LinearLayout,RelativeLayout,FrameLayout,TableLayout,FlowLayout,FloatLayout,PathLayout,GridLayout,LayoutSizeClass to build your App 自动布局 UIView UITableView UICollectionView RTL

Updated Jul 26, 2021
Objective-C

chisel3

chipsalliance / chisel3

Open

Inconsistency with Decoupled and DecoupledIO

1

mwachs5 commented Mar 7, 2022

It's a source of confusion when to use Decoupled and when to use DecoupledI

Read more

good first issue

Open

Add Bundle.Init (analogous to VecInit / Bundle.Lit)

3

Open

We have no documentation/training on `Mem`

3

Find more good first issues

chipsalliance / rocket-chip

Rocket Chip Generator

scala rocket-chip chip-generator chisel riscv rtl

Updated Mar 23, 2022
Scala

layoutBox / PinLayout

Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]

swift language swift-library ios cocoapod layout carthage layout-engine rtl swift-framework swift-3 ios-swift anchor ios-ui ios-lib margin chainable-methods uiview-extension left-language

Updated Feb 8, 2022
Swift

MohammadYounes / rtlcss

Framework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)

javascript css i18n postcss css3 mirror donation ltr rtl cascading-style-sheets postcss-plugin flip rtlcss right-to-left left-to-right

Updated Mar 1, 2022
JavaScript

darklife / darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

cpu fpga core processor riscv rtl verilog risc-v rv32i softcore processor-design rv32e

Updated Jan 16, 2022
Verilog

riscv-boom / riscv-boom

Open

V extension support

siyy123 commented Apr 5, 2021

Type of issue: feature request

Impact: new rtl

Development Phase: request

Other information
As the vector extension proposal is near stable and the necessary things is defined in the rocket chip repo I think now the vector e

Read more

missing feature good first issue

Open

Add chicken-bit support to BOOM

4

kartik-v / bootstrap-star-rating

A simple yet powerful JQuery star rating plugin with fractional rating support.

javascript css jquery rating css-styles rtl caption star bootstrap-star-rating rate-control change-stars star-symbols fractional

Updated Jan 20, 2022
JavaScript

SpinalHDL / SpinalHDL

Scala based HDL

scala fpga vhdl rtl verilog

Updated Mar 24, 2022
Scala

ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

boom rocket rocket-chip chip-generator chisel riscv rtl peripherals soc out-of-order superscalar risc-v firesim accelerators chipyard hwacha

Updated Mar 23, 2022
C

eldraco / Salamandra

Salamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.

python threshold microphone sound rtl sdr microphones spy spy-microphones salamandra find-microphones detect-microphones

Updated Jan 11, 2021
Python

Leku

AdevintaSpain / Leku

🌍 Map location picker component for Android. Based on Google Maps. An alternative to Google Place Picker.

Updated Mar 15, 2022
Kotlin

chipsalliance / Cores-SweRV

SweRV EH1 core

fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design swerv swerv-eh1

Updated Jan 27, 2022
SystemVerilog

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Updated Mar 24, 2022
Verilog

The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow

cpp tcl eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

Updated Mar 24, 2022
Verilog

syntacore / scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

core riscv rtl ip verilog risc-v rv32i rv32e rv32imc rv32emc

Updated Jan 19, 2022
SystemVerilog

bootstrap-v4-rtl

MahdiMajidzadeh / bootstrap-v4-rtl

RTL edition of bootstrap v4 for rtl languages like Farsi and Arabic

bootstrap css-framework rtl persian arabic farsi right-to-left rtl-edition

Updated Mar 15, 2022
JavaScript

pulp-platform / axi

Open

Add AXI FIFO

andreaskurth commented Dec 8, 2021

We have axi_cut and axi_multicut for pipelining (to be unified), but we currently don't have a module for buffering AXI beats in FIFOs. This gap can be filled by a new axi_fifo module.

Implementing thi

Read more

enhancement good first issue

fondesa / recycler-view-divider

A library which configures a divider for a RecyclerView.

android list recyclerview rtl staggeredgrid divider linearlayoutmanager gridlayoutmanager itemdecoration staggeredgridlayoutmanager divideritemdecoration staggered androidx

Updated Feb 3, 2022
Kotlin

seldridge / verilog

Repository for basic (and not so basic) Verilog blocks with high re-use potential

fpga hardware rtl verilog

Updated Mar 15, 2018
Verilog

ultraembedded / cores

Sponsor

Various HDL (Verilog) IP Cores

audio asic fpga usb rtl verilog spi sram uart verilog-hdl verilog-components verilator i2s sdram

Updated Jul 1, 2021
Verilog

01walid / awesome-arabic

A curated list of awesome projects and dev/design resources for supporting Arabic computational needs.

nlp natural-language-processing rtl arabic nlp-arabic

Updated Oct 20, 2021

open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

linux fpga zynq hls hardware vhdl rtl verilog xilinx sdr wi-fi analog-devices ieee80211 dma software-defined-radio ofdm csma ad9361 mac80211

Updated Mar 24, 2022
Verilog

duolingo / rtl-viewpager

ViewPager with RTL support 🔄

android viewpager rtl

Updated Feb 15, 2021
Java

ucb-bar / riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

chisel riscv rtl

Updated Mar 3, 2022
Scala

react-datepicker

tomgreenwood1 / react-datepicker

An easily internationalizable, accessible, mobile-friendly datepicker library for the web, build with styled-components.

react i18n typescript grid styled-components datepicker rtl styled-system react-hooks

Updated Oct 23, 2021
JavaScript

framevuerk

framevuerk / framevuerk

Fast, Responsive, Multi Language, Both Direction Support and Configurable UI Framework based on Vue.js.

javascript framework ui vue js toolkit responsive ux ltr rtl multi-language configurable multilanguage

Updated Feb 26, 2022
Vue

Nuand / bladeRF-wiphy

bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

vhdl rtl hdl ofdm bladerf ofdm-wireless-communications 80211 dsss

Updated Feb 26, 2022
VHDL

tailwindcss-rtl

20lives / tailwindcss-rtl

Enabling bidirectional support on tailwindcss framework

css ltr rtl logical direction tailwindcss tailwindcss-rtl

Updated Feb 16, 2022
JavaScript

wayfair-archive / awesome-learning

Awesome Learning - Learn JavaScript and Front-End Fundamentals at your own pace

react javascript learning education enzyme frontend jest reactjs scss rtl learning-materials codesandbox gatsbyjs

Updated Jan 15, 2022
JavaScript

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