zephyrproject-rtos · carlescufi · Nov 18, 2021 · Jan 6, 2021 · Jan 7, 2021 · Jan 7, 2021
@@ -232,6 +232,7 @@ enum node_rx_type {
 	NODE_RX_TYPE_SYNC_LOST,
 	NODE_RX_TYPE_SYNC_CHM_COMPLETE,
 	NODE_RX_TYPE_SYNC_ISO,
+	NODE_RX_TYPE_SYNC_ISO_PDU,
 	NODE_RX_TYPE_SYNC_ISO_LOST,
 	NODE_RX_TYPE_EXT_ADV_TERMINATE,
 	NODE_RX_TYPE_BIG_COMPLETE,
@@ -328,6 +329,9 @@ struct node_rx_iso_meta {
 /* Define invalid/unassigned Controller LLL context handle */
 #define LLL_HANDLE_INVALID     0xFFFF
 
+/* Define invalid/unassigned Controller Advertising LLL context handle */
+#define LLL_ADV_HANDLE_INVALID 0xFF
+
 /* Header of node_rx_pdu */
 struct node_rx_hdr {
 	union {
@@ -374,6 +378,10 @@ enum {
 #if defined(CONFIG_BT_BROADCASTER)
 	EVENT_DONE_EXTRA_TYPE_ADV,
 	EVENT_DONE_EXTRA_TYPE_ADV_AUX,
+#if defined(CONFIG_BT_CTLR_ADV_ISO)
+	EVENT_DONE_EXTRA_TYPE_ADV_ISO_COMPLETE,
+	EVENT_DONE_EXTRA_TYPE_ADV_ISO_TERMINATE,
+#endif /* CONFIG_BT_CTLR_ADV_ISO */
 #endif /* CONFIG_BT_BROADCASTER */
 #endif /* CONFIG_BT_CTLR_ADV_EXT || CONFIG_BT_CTLR_JIT_SCHEDULING */
 
@@ -383,6 +391,11 @@ enum {
 	EVENT_DONE_EXTRA_TYPE_SCAN_AUX,
 #if defined(CONFIG_BT_CTLR_SYNC_PERIODIC)
 	EVENT_DONE_EXTRA_TYPE_SYNC,
+#if defined(CONFIG_BT_CTLR_SYNC_ISO)
+	EVENT_DONE_EXTRA_TYPE_SYNC_ISO_ESTAB,
+	EVENT_DONE_EXTRA_TYPE_SYNC_ISO,
+	EVENT_DONE_EXTRA_TYPE_SYNC_ISO_TERMINATE,
+#endif /* CONFIG_BT_CTLR_SYNC_ISO */
 #endif /* CONFIG_BT_CTLR_SYNC_PERIODIC */
 #endif /* CONFIG_BT_CTLR_ADV_EXT */
 #endif /* CONFIG_BT_OBSERVER */

@@ -7,6 +7,54 @@
 struct lll_adv_iso {
 	struct lll_hdr hdr;
 	struct lll_adv *adv;
+
+	uint8_t seed_access_addr[4];
+	uint8_t base_crc_init[2];
+	uint16_t latency_prepare;
+	uint16_t latency_event;
+	uint16_t data_chan_prn_s;
+	uint16_t data_chan_remap_idx;
+
+	uint64_t payload_count:39;
+	uint64_t enc:1;
+	uint64_t framing:1;
+	uint64_t handle:8;
+	uint64_t cssn:3;
+
+	uint8_t data_chan_map[5];
+	uint8_t data_chan_count:6;
+	uint8_t num_bis:5;
+	uint8_t bn:3;
+	uint8_t nse:5;
+	uint8_t phy:3;
+
+	uint32_t sub_interval:20;
+	uint32_t max_pdu:8;
+	uint32_t pto:4;
+
+	uint32_t bis_spacing:20;
+	uint32_t max_sdu:8;
+	uint32_t irc:4;
+
+	uint32_t sdu_interval:20;
+	uint32_t irc_curr:4;
+	uint32_t ptc_curr:4;
+	uint32_t ptc:4;
+
+	uint8_t bn_curr:3;
+	uint8_t bis_curr:5;
+
+	uint8_t phy_flags:1;
+
+	uint8_t term_req:1;
+	uint8_t term_ack:1;
+	uint8_t term_reason;
+	uint8_t chm_req;
+	uint8_t chm_ack;
+
+	uint8_t  ctrl_chan_use;
+	uint8_t  ctrl_expire;
+	uint16_t ctrl_instant;
 };
 
 struct lll_adv_sync {

@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2021 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+int lll_adv_iso_init(void);
+int lll_adv_iso_reset(void);
+void lll_adv_iso_create_prepare(void *param);
+void lll_adv_iso_prepare(void *param);
@@ -27,6 +27,10 @@ struct lll_sync {
 	uint8_t filter_policy:1;
 	uint8_t is_aux_sched:1;
 
+#if defined(CONFIG_BT_CTLR_SYNC_ISO)
+	uint8_t sca:3;
+#endif /* CONFIG_BT_CTLR_SYNC_ISO */
+
 	uint16_t skip_prepare;
 	uint16_t skip_event;
 	uint16_t event_counter;

@@ -1,9 +1,69 @@
 /*
- * Copyright (c) 2020 Nordic Semiconductor ASA
+ * Copyright (c) 2020-2021 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 struct lll_sync_iso {
 	struct lll_hdr hdr;
+
+	uint8_t seed_access_addr[4];
+	uint8_t base_crc_init[2];
+
+	uint16_t latency_prepare;
+	uint16_t latency_event;
+	uint16_t data_chan_prn_s;
+	uint16_t data_chan_remap_idx;
+
+	uint64_t payload_count:39;
+	uint64_t enc:1;
+	uint64_t ctrl:1;
+	uint64_t cssn_curr:3;
+	uint64_t cssn_next:3;
+
+	uint8_t data_chan_map[5];
+	uint8_t data_chan_count:6;
+	uint8_t num_bis:5;
+	uint8_t bn:3;
+	uint8_t nse:5;
+	uint8_t phy:3;
+
+	uint32_t sub_interval:20;
+	uint32_t max_pdu:8;
+	uint32_t pto:4;
+
+	uint32_t bis_spacing:20;
+	uint32_t max_sdu:8;
+	uint32_t irc:4;
+
+	uint32_t sdu_interval:20;
+	uint32_t irc_curr:4;
+	uint32_t ptc_curr:4;
+	uint32_t ptc:4;
+
+	uint8_t bn_curr:3;
+	uint8_t bis_curr:5;
+
+	uint8_t term_reason;
+
+	uint8_t ctrl_chan_use;
+	uint16_t ctrl_instant;
+
+	struct node_rx_pdu *payload[PDU_BIG_PAYLOAD_COUNT_MAX];
+	uint8_t payload_count_max;
+	uint8_t payload_head;
+	uint8_t payload_tail;
+
+	uint32_t window_widening_periodic_us;
+	uint32_t window_widening_max_us;
+	uint32_t window_widening_prepare_us;
+	uint32_t window_widening_event_us;
+	uint32_t window_size_event_us;
 };
+
+int lll_sync_iso_init(void);
+int lll_sync_iso_reset(void);
+void lll_sync_iso_create_prepare(void *param);
+void lll_sync_iso_prepare(void *param);
+
+extern uint8_t ull_sync_iso_lll_handle_get(struct lll_sync_iso *lll);
@@ -83,9 +83,9 @@ static inline bool isr_rx_ci_adva_check(uint8_t tx_addr, uint8_t *addr,
 					struct pdu_adv *ci);
 
 #if defined(CONFIG_BT_CTLR_ADV_EXT)
-#define PAYLOAD_BASED_FRAG_COUNT ((CONFIG_BT_CTLR_ADV_DATA_LEN_MAX + \
-				   PDU_AC_PAYLOAD_SIZE_MAX - 1) / \
-				  PDU_AC_PAYLOAD_SIZE_MAX)
+#define PAYLOAD_BASED_FRAG_COUNT \
+	ceiling_fraction(CONFIG_BT_CTLR_ADV_DATA_LEN_MAX, \
+			 PDU_AC_PAYLOAD_SIZE_MAX)
 #define PAYLOAD_FRAG_COUNT MAX(PAYLOAD_BASED_FRAG_COUNT, BT_CTLR_DF_PER_ADV_CTE_NUM_MAX)
 #define BT_CTLR_ADV_AUX_SET  CONFIG_BT_CTLR_ADV_AUX_SET
 #if defined(CONFIG_BT_CTLR_ADV_PERIODIC)

@@ -50,18 +50,6 @@ lll_adv_sync_data_latest_get(struct lll_adv_sync *lll, void **extra_data,
 	return lll_adv_pdu_latest_get(&lll->data, is_modified);
 #endif /* CONFIG_BT_CTLR_ADV_EXT_PDU_EXTRA_DATA_MEMORY */
 }
-
-static inline struct pdu_adv *
-lll_adv_sync_data_curr_get(struct lll_adv_sync *lll, void **extra_data)
-{
-	uint8_t first = lll->data.first;
-#if defined(CONFIG_BT_CTLR_ADV_EXT_PDU_EXTRA_DATA_MEMORY)
-	if (extra_data) {
-		*extra_data = lll->data.extra_data[first];
-	}
-#endif /* CONFIG_BT_CTLR_ADV_EXT_PDU_EXTRA_DATA_MEMORY */
-	return (void *)lll->data.pdu[first];
-}
 #endif /* CONFIG_BT_CTLR_ADV_PERIODIC */
 #endif /* CONFIG_BT_CTLR_ADV_EXT */