Chisel 3: A Modern Hardware Design Language
Scala 2.4k 431
Rocket Chip Generator
Scala 2.2k 827
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.
C++ 600 115
SweRV EH1 core
SystemVerilog 538 134
Flexible Intermediate Representation for RTL
Scala 514 154
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
C++ 200 42
Output of the sv-tests runs.
FPGA tool performance profiling
Test suite designed to check compliance with the SystemVerilog standard.
Documentation for F4PGA
The specification for the FIRRTL language
Repository to run extensive tests on the FPGA interchange format
