#
rocket-chip
Here are 21 public repositories matching this topic...
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
boom
rocket
rocket-chip
chip-generator
chisel
riscv
rtl
peripherals
soc
out-of-order
superscalar
risc-v
firesim
accelerators
chipyard
hwacha
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Feb 16, 2022 - C
abejgonzalez
commented
Jan 20, 2020
This is discussed a bit more in #456.
Currently, to copy off files from the fs is to 1. mount, 2. chattr, 3. chmod/chown, 4. copy files off. However, this is destructive to the fs (since it changes permissions/users). Instead, there should be a less invasive way to copy off files that doesn't mess with the underlying fs so that people can copy the fs and use it somewhere else.
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
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Jan 23, 2020 - Scala
RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
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Nov 14, 2018 - SystemVerilog
Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.
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Nov 24, 2019 - C
C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
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Jul 14, 2020 - C
Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
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Nov 3, 2021 - Tcl
A fault-injection framework using Chisel and FIRRTL
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Sep 4, 2018 - Scala
This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 SoC is Hex Five's official reference platform for its MultiZone Security Trusted Execution Environment and MultiZone Security Trusted Firmware. The X300 is an enhanced secure version of the - now archived - SiFive's Freedom E300 Platform built around the RISC-V Rocket chip originally developed at U.C. Berkeley.
fpga
rocket-chip
xilinx
fpga-soc
risc-v
xilinx-fpga
bitstream
digilent
e300
artix-100t
sifive-freedom
arty-a7
artix-35t
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Oct 19, 2021 - Scala
Network components (NIC, Switch) for FireBox
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Feb 11, 2022 - Scala
BOOM's Simulation Accelerator.
simulation
accelerator
boom
rocket
rocket-chip
chisel
riscv
rtl
firrtl
soc
risc-v
verilator
chipyard
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Dec 16, 2021 - Scala
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Jan 9, 2021 - Scala
Parallella RISC-V Prebuilt Images
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Aug 18, 2016
A simple baremetal program template for RISC-V inspired from riscv benchmark tests
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Apr 17, 2018 - C
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Type of issue: feature request
Impact: new rtl
Development Phase: request
Other information
As the vector extension proposal is near stable and the necessary things is defined in the rocket chip repo I think now the vector e