rv32im

RISC-V CPU Core (RV32IM)

32-bit Superscalar RISC-V CPU

A self-hosting and educational C compiler

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

Simple 3-stage pipeline RISC-V processor

Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice

Trivial RISC-V Linux binary bootloader

A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.

miniSpartan6+ (Spartan6) FPGA based MP3 Player

Some materials and sample source for RV32 OS projects.

The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pipeline CPU supports the entire RV32IM ISA which contains 45 instructions. The designed pipeline CPU was implemented using behavioral modeling in verilogHDL and icarus Verilog was used compile and simulate. gtkWave was used to observe the behavior.

RISC-V Linux Port (supporting RV32IM - CPUs without atomic extensions)

RV32IM System-on-Chip (SoC)

RISC-V 5-stage pipeline RV32I implementation with forwarding in verilog with drivers to work on xilinx nexus a7 FPGA boards

TangNano-9K-example project with kianRiscV cpu

Attempt at building entirely from scratch a RISC-V SoC for self-education purposes.

herve, the rv simulator is a simple risc-v RV32IMA ISA simulator.

sysy lang by c executable in risc-v platform.