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systemverilog
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Test case
typedef dv_base_env_cov #(.CFG_T(tl_agent_env_cfg)) tl_agent_env_cov;Actual output
typedef dv_base_env_cov#(.CFG_T(tl_agent_env_cfg)) tl_agent_env_cov;Expected or suggested output (original formatting)
typedef dv_base_env_cov #(.CFG_T(tl_agent_env_cfg)) tl_agent_env_cov;Verible version:
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Nov 25, 2019 - SystemVerilog
When running the regression, the resulting logs seem to end up in third_party/tests/$TEST/.... This of course is not unnoticed by git, so a git status shows a ton of non-added new files added.
To reproduce:
make
make regression
git status # observe all the filesBuild or test artifacts should never clutter the rest of the code-base (we should regard them as read-only in
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Oct 22, 2021 - Verilog
Here are some "nice to have" feature requests for the cool new "Compared test results" output that has been recently added.
- Colors! It would be nice to highlight;
- Improvements in green
- Regressions in red.
- Non-changes de-emphasized in light grey.
- Link to the published version of the before and after results so people can understand exactly
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Aug 14, 2021 - Python
- AxProt[0]
- 0: Unprivileged access
- 1: Privileged access
- AxProt[1]
- Secure access
- Non-secure access
- AxProt[2]
- Data access
- Instruction access
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If you speak another language, I would appreciate your help in translating the
README.md.For tables, checklists, or other data that might change, please indicate that that information is in the main README. Otherwise every change to the main README will need to be replicated to the other READMEs.
^ I've tried to do this a bit in the French README. The only thing you need to replicate when