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asic

Here are 150 public repositories matching this topic...

skywater-pdk

google / skywater-pdk

Star

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

magic asic eda pdk asic-library openroad openram skywater

Updated Sep 28, 2021
Python

openhwgroup / cva6

Star

Open

64 bit addresses must have bits 63-39 cleared

zarubaf commented Feb 3, 2020

If this is not the case a page fault should be generated. Right now we generate an instruction access fault.

https://github.com/pulp-platform/ariane/blob/ad70ce1f30dad539e5a365ffe71a02aaf20b397e/src/load_store_unit.sv#L339

Read more

Component:RTL Good First Issue

clash-lang / clash-compiler

Star

Haskell to VHDL/Verilog/SystemVerilog compiler

haskell asic fpga vhdl verilog systemverilog hardware-description-language

Updated Oct 8, 2021
Haskell

riscvarchive / riscv-cores-list

Star

RISC-V Cores, SoC platforms and SoCs

asic fpga risc-v socs open-isa

Updated Mar 26, 2021

serv

olofk / serv

Star

SERV - The SErial RISC-V CPU

asic fpga verilog risc-v

Updated Oct 3, 2021
Verilog

ZhishengWang / Embedded-Neural-Network

Star

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

compression asic university fpga deep-learning neural-network stanford-university harvard-university

Updated Apr 11, 2019

VUnit / vunit

Star

Open

What child process is VUnit being unable to create?

3

curiousengineer commented Dec 1, 2020

Here is the problem:

$ make compile
Traceback (most recent call last):
File "C:\My_Designs\probe_fpga_design_1\run.py", line 336, in
main()
File "C:\My_Designs\probe_fpga_design_1\run.py", line 181, in main
vu.add_osvvm()
File "c:\my_designs\probe_fpga_design_1\deps\vunit\vunit\ui_init_.py", line 1030, in add_osvvm
self.builtins.add("osvvm")
File "c:\my

Read more

enhancement simulator support good first issue

Open

VUnit.add_source_files_from_csv() does not allow for all kwargs to be used

2

Open

SystemVerilog: Get current test name

8

esig / dss

Star

Digital Signature Service : creation, extension and validation of advanced electronic signatures

java asic validation signature xades cades pades esignature jades

Updated Sep 20, 2021
Java

The-OpenROAD-Project / OpenLane

Star

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Updated Oct 8, 2021
Verilog

VLSI-EDA / PoC

Star

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Updated Nov 29, 2020
VHDL

ultraembedded / riscv

Sponsor Star

RISC-V CPU Core (RV32IM)

asic cpu fpga verification verilog pipeline-processor risc-v rv32i verilator riscv-linux rv32im

Updated Sep 18, 2021
Verilog

ultraembedded / cores

Sponsor Star

Various HDL (Verilog) IP Cores

audio asic fpga usb rtl verilog spi sram uart verilog-hdl verilog-components verilator i2s sdram

Updated Jul 1, 2021
Verilog

pulp-platform / axi

Star

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic fpga hardware rtl ip systemverilog axi network-on-chip axi4 axi4-lite

Updated Oct 8, 2021
SystemVerilog

ultraembedded / biriscv

Sponsor Star

32-bit Superscalar RISC-V CPU

linux asic cpu fpga verilog xilinx superscalar in-order risc-v branch-prediction coremark rv32i verilator riscv-linux rv32im artix-7 pipelined-processors

Updated Sep 18, 2021
Verilog

furrtek / DMG-CPU-Inside

Star

Reverse-engineered schematics for DMG-CPU-B

nintendo asic gameboy electronics reverse-engineering chip schematics game-boy silicon dmg-001

Updated Nov 30, 2020

anselal / antminer-monitor

Star

Open

Integration of EthOS miner API in Antminer-Monitor-Master App

A-RK6 commented Jan 10, 2018

Broadening the horizons of the Antminer-Monitor-Master App makes perfect sense now that GPU mining is becoming more and more popular.

At present, EthOS have over 50,000 miners working with their OS so their software is well developed and regularly maintained.

An example of the EthOS monitor can be found here: 48061f.ethosdistro.com

Example API:

{"rigs":{"91c5eb":{"condition":"high_lo

Read more

good first issue ⭐ feature request

Open

Control

12

tymonx / logic

Star

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

cmake asic fpga cpp verification rtl verilog xilinx vivado systemverilog systemc unit-tests hdl modelsim uvm verilator quartus testing-rtl

Updated Nov 25, 2019
SystemVerilog

secworks / aes

Star

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

asic encryption fpga aes block-cipher

Updated May 12, 2021
Verilog

Juniper / open-register-design-tool

Star

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

asic fpga eda systemverilog uvm registers systemrdl jspec register-descriptions systemrdl-compiler

Updated Oct 19, 2020
Verilog

SystemRDL / systemrdl-compiler

Star

SystemRDL 2.0 language compiler front-end

asic fpga eda registers register-descriptions systemrdl-compiler hardware-description-language design-automation register-description-language

Updated Oct 7, 2021
C++

masc-ucsc / livehd

Star

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

asic fpga simulation live synthesis hdl lgraph

Updated Oct 8, 2021
Verilog

minershive / hiveos-asic

Star

Hive OS client for ASICs

asic bitcoin mining litecoin

Updated Oct 6, 2021
Shell

rggen / rggen

Star

Code generation tool for configuration and status registers

asic fpga vhdl eda rtl verilog csr systemverilog soc uvm ral axi amba apb register-descriptions uvm-ral-model uvm-register-model wiki-documents

Updated May 22, 2021
Ruby

furrtek / VGChips

Star

Video Game custom chips reverse-engineered from silicon

asic fpga reverse-engineering arcade verilog chip hdl silicon cpld repro taito decap

Updated Sep 20, 2021
Verilog

lakshmi-sathi / avsdpll_1v8

Star

8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

asic ic intellectual-property pll analog-circuit rtl2gds clock-multiplier phase-detector charge-pump manufacturable

Updated Jul 31, 2021

pulp-platform / ara

Star

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

asic cpu vector riscv ara rvv rv64gcv

Updated Oct 8, 2021
C

troyguo / awesome-dv

Star

Awesome ASIC design verification

asic verification uvm formal-verification asic-verification

Updated Dec 29, 2020

unihd-cag / skillbridge

Star

A seamless python to Cadence Virtuoso Skill interface

python asic hardware skill cadence-virtuoso cadence virtuoso design-automation skillbridge

Updated Jul 9, 2021
Python

trilomix / GDS3D

Star

GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called process definition file which contains the 3D parameters of the process being used. These files combined allow the program to create a 3D representation of the layout, where the user has full, real time control over the camera position and angle, much like in a 3D video game. An other repo (https://github.com/skuep/GDS3D) as the same source and add few improvement like compression with server/client process. This release add two major feature with are assembly and export 3D model for GMSH. Assembly: this mean it’s possible to merge multi GDS (with different technologies) I also try to improve net highlight.

asic eda mesh fem 3d-models integrated-circuits gdsii

Updated May 19, 2021
C++

pulp-platform / mempool

Star

A 256-RISC-V-core system with low-latency access into shared L1 memory.

asic risc-v manycore

Updated Sep 28, 2021
C

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