The Wayback Machine - https://web.archive.org/web/20210724224933/https://github.com/topics/xilinx

#

xilinx

Here are 396 public repositories matching this topic...

open-sdr / openwifi

Star

open-source 802.11 WiFi baseband chip/FPGA design

linux fpga zynq hls wifi verilog xilinx sdr analog-devices ieee80211 xilinx-fpga dma software-defined-radio ofdm csma ad9361 802-11 mac80211 openwifi

Updated Jul 16, 2021
C

hdl-util / hdmi

Star

Open

Translate README.md

sameer commented May 16, 2020

If you speak another language, I would appreciate your help in translating the README.md.

For tables, checklists, or other data that might change, please indicate that that information is in the main README. Otherwise every change to the main README will need to be replicated to the other READMEs.

^ I've tried to do this a bit in the French README. The only thing you need to replicate when

Read more

good first issue help wanted

prjxray

SymbiFlow / prjxray

Star

Open

Assign xc7 prefix to prjxray tools to avoid conflicts

4

acomodi commented May 25, 2020

All the tools in prjxray should have an xc7 prefix, so to make them unique.

E.g. bitread or bittool could enter in conflicts with other tools names.

Read more

good first issue

Open

Document remaining bits in opentitan bitstream

3

Open

Refactor xjson library

Find more good first issues →

Xilinx / brevitas

Star

Brevitas: quantization-aware training in PyTorch

text-to-speech fpga pytorch speech-recognition neural-networks image-classification xilinx quantization hardware-acceleration brevitas

Updated Jul 20, 2021
Python

trivialmips / nontrivial-mips

Star

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

cpu fpga mips xilinx fpga-soc-linux systemverilog fpga-soc

Updated Jul 7, 2020
SystemVerilog

VLSI-EDA / PoC

Star

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Updated Nov 29, 2020
VHDL

Cr4sh / s6_pcie_microblaze

Star

PCI Express DIY hacking toolkit for Xilinx SP605

kernel fpga backdoor rootkit hypervisor uefi xilinx hyper-v dma microblaze pci-e

Updated May 26, 2021
C

trabucayre / openFPGALoader

Star

Universal utility for programming FPGA

fpga intel cyclone xilinx lattice bitstream arty gowin trenz-gowin-littlebee

Updated Jul 21, 2021
C++

f32c / f32c

Star

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

arduino fpga mips riscv xilinx altera lattice

Updated Jul 23, 2020
VHDL

LeiWang1999 / FPGA

Star

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga verilog xilinx vivado pynq

Updated Jun 27, 2021

Xilinx / SDAccel_Examples

Star

SDAccel Examples

c aws fpga cpp opencl xilinx sdx sdaccel nimbix

Updated Jul 16, 2020
C++

olofk / edalize

Star

An abstraction library for interfacing EDA tools

Updated Jul 14, 2021
Python

pConst / basic_verilog

Star

Must-have verilog systemverilog modules

Updated Jul 18, 2021
Verilog

ultraembedded / biriscv

Sponsor Star

32-bit Superscalar RISC-V CPU

linux asic cpu fpga verilog xilinx superscalar in-order risc-v branch-prediction coremark rv32i verilator riscv-linux rv32im artix-7 pipelined-processors

Updated Jul 19, 2021
Verilog

Xilinx / CHaiDNN

Star

HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs

deep-neural-networks inference dnn xilinx alexnet googlenet embedded-vision xilinx-ultrascale-mpsocs

Updated Jul 9, 2019
C++

bperez77 / xilinx_axidma

Star

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.

fpga driver xilinx zedboard axi-dma linux-driver axi-vdma dma-driver xilinx-axi-dma xilinx-axi-vdma userspace-dma fpga-dma

Updated Jan 4, 2021
C

open-sdr / openwifi-hw

Star

FPGA/hardware design of openwifi

linux fpga zynq hls verilog xilinx sdr vivado wi-fi analog-devices ieee80211 dma software-defined-radio ofdm csma ad9361 802-11 mac80211 openwifi

Updated Jul 19, 2021
Verilog

pavel-demin / red-pitaya-notes

Star

Notes on the Red Pitaya Open Source Instrument

radio linux fpga zynq dsp tcl verilog nmr xilinx sdr mca redpitaya vna vivado wspr red-pitaya vitis

Updated Jul 7, 2021
C

ZipCPU / wb2axip

Star

Bus bridges and other odds and ends

fpga gplv3 xilinx wishbone xilinx-vivado wishbone-bus axi-bus

Updated Jun 28, 2021
Verilog

Vitis_Accel_Examples

Xilinx / Vitis_Accel_Examples

Star

Vitis_Accel_Examples

zynq xilinx soc alveo fpga-programming acap vitis

Updated Jul 2, 2021
C++

lastweek / fpga_readings

Star

Recipe for FPGA cooking

fpga hls rtl verilog xilinx vivado-hls

Updated Jul 14, 2021
Verilog

jofrfu / tinyTPU

Star

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Updated Jan 5, 2019
VHDL

Xilinx / RapidWright

Star

Build Customized FPGA Implementations for Vivado

fpga xilinx vivado rapidwright

Updated Jul 23, 2021
Java

tymonx / logic

Star

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

cmake asic fpga cpp verification rtl verilog xilinx vivado systemverilog systemc unit-tests hdl modelsim uvm verilator quartus testing-rtl

Updated Nov 25, 2019
SystemVerilog

definelicht / hlslib

Star

A collection of extensions for Vivado HLS and Intel FPGA OpenCL to improve developer quality of life.

cmake fpga hpc xilinx sdaccel high-level-synthesis vivado-hls intel-fpga vitis intel-fpga-opencl

Updated Jul 2, 2021
C++

suoto / hdl_checker

Star

Repurposing existing HDL tools to help writing better code

python vim language-server vhdl issue-tracker standalone verilog xilinx syntax-checker systemverilog trademarks hdl modelsim questasim ghdl xilinx-vivado lsp-server coc-nvim vim-ale vivado-simulator mentor-msim hdl-checker emacs-lsp

Updated Jul 24, 2021
Python

eugene-tarassov / vivado-risc-v

Star

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

linux fpga boom xilinx vivado risc-v nexys-video vc707 rocketchip genesys2 kc705

Updated Jul 14, 2021
C

trivialmips / TrivialMIPS

Star

MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support

cpu fpga mips xilinx systemverilog fpga-soc

Updated Apr 29, 2019
SystemVerilog

Xtra-Computing / ThunderGP

Star

Open

Accessing Properties of Vertices with Null Out-Degree

10

pfsi commented Mar 22, 2021

Hi everyone.

I'm wondering about accessing the property of vertices with out-degree equal to 0.
I understand these are somehow filtered out of certain computations since they generate no updates, but they should still receive updates so I'd like to access their property after some number of supersteps.

I would also appreciate an explanation on the various MEM_ID pointers.

Read more

good first issue

jeremytrimble / ezdma

Star

Simple, zero-copy DMA to/from userspace.

linux zynq xilinx dma xilinx-axi-dma

Updated Sep 18, 2017
C

Improve this page

Add a description, image, and links to the xilinx topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the xilinx topic, visit your repo's landing page and select "manage topics."