lowRISC / opentitan
OpenTitan: Open source silicon root of trust
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OpenTitan: Open source silicon root of trust
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
AXI X-Bar
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Pipelines the AXI path with FIFOs
Common SystemVerilog components
open-source Ethenet media access controller for Ariane on Genesys-2
IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs
[UNRELEASED] FP div/sqrt unit for transprecision
Simple single-port AXI memory interface
Generic Register Interface (contains various adatpers)
AXI Adapter(s) for RISC-V Atomic Operations
RISC-V Debug Support for our PULP RISC-V Cores
APB Timer Unit
Lean but mean RISC-V system!
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.