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TTL-RISC-VPublic
RISC-V processor & peripherals made (almost) entirely with 74-series TTL logic chips.
Python 1
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202 contributions in the last year
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Contribution activity
November 2021
Created 17 commits in 4 repositories
Reviewed 6 pull requests in 1 repository
bytedance/sonic
6 pull requests
- feat: add PretouchRec() to speed up the first time in JIT for large/deep struct
- test: fix timeout problem in issue_test when enable force GC
- fix: add gc_write_barrier checks
- fix: set _Stack.sp zero whenever put into pool
- fix: add stack memory at _VAR_vp to pass the address of vp while recu…
- fix: use stackmap of shadow func as jit func's
Created an issue in logisim-evolution/logisim-evolution that received 11 comments
Create and edit the appearance of a sub-circuit in v3.7.1 doesn't work as expected
Expected behavior:
Open a .circ file created with a version before v3.7.1
Create a new sub-circuit
Edit it's appearance
Add the sub-circuit into m…
11
comments

