Pinned

1. friscv

   RISCV CPU implementation in SystemVerilog

   SystemVerilog 1 1

2. vim-leader-mapper

   Vim plugin to create Neovim leader key menu

   Vim script 42 2

3. svut

   SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

   Python 22 5

4. bster

   Implementation of a binary search tree algorithm in a FPGA/ASIC IP

   SystemVerilog 1

5. meduram

   Multi-port BRAM IP for ASIC and FPGA

   SystemVerilog 2

6. async_fifo

   A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

   Verilog 67 30