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Language: Verilog
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SymbiFlow / symbiflow-examples
Example designs showing different ways to use SymbiFlow toolchains.
bespoke-silicon-group / basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
The-OpenROAD-Project / OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow
IObundle / iob-cache
Verilog configurable cache
IObundle / iob-picorv32
IOb_SoC version of the Picorv32 RISC-V Verilog IP core
ucb-bar / nvdla-wrapper
Wraps the NVDLA project for Chipyard integration
pConst / basic_verilog
Must-have verilog systemverilog modules
SI-RISCV / e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
ucb-bar / sha3
IObundle / iob-interconnect
handle bus interconnection
analogdevicesinc / hdl
HDL libraries and projects
cliffordwolf / picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
alexforencich / verilog-axi
Verilog AXI components for FPGA implementation

