microarchitecture

A cross platform C99 library to get cpu features at runtime.

Open-source high-performance RISC-V processor

Simple yet fancy CPU architecture fetching tool

inVtero.net: A high speed (Gbps) Forensics, Memory integrity & assurance. Includes offensive & defensive memory capabilities. Find/Extract processes, hypervisors (including nested) in memory dumps using microarchitechture independent Virtual Machiene Introspection techniques

High performance Bitcoin development platform

Microbenchmark to achieve peak performance on x86_64 CPUs and NVIDIA GPUs

Microarchitectural exploitation and other hardware attacks.

A small RISC-V core (SystemVerilog)

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64

Performance Counter Measurements at the cycle granularity

Sequential entries of a long number with offset for the FPGA microarchitecture on system verilog

💻 Custom 64-bit pipelined RISC processor.

One Instruction Set Computer

💻 Dual-core 16-bit RISC processor.

A small RISC-V core (VHDL)

Virtualization of a 32-bit ARM-like processor with native execution.

An implementation of the LC-3 architecture in VHDL, as described in the book "Introduction to Computing Systems by P&P".

[2009 – 2012] MDSP: functional simulation of a Multimedia Digital Signal Processor

DSCP is a dynamic secure cache partitioning implementation on gem5. The code includes a ScatterCache (USENIX SECURITY'19) variant and it is partially available to reproduce set partitioning.

A cross platform Redis Module Example that warns and uses the optimized functions based on instruction set extensions available and or microarchitecture

A real time computing machine

💻 Simple 16-bit RISC processor.

Presentation about software-based Micro-architectural Side-Channel attacks.

A pedagogical processor on FPGA, developed at NIIT University.

💻 Simple accumulator-based 4-bit processor.

some tlb experimentation code: calculate L1, L2 miss penalties and show cross-HT interference.

riscv_myth_workshop created by GitHub Classroom. Contains an implemented RISC-V 32-bit core.