Repositories
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core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
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cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
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cv32e40x
4 stage, in-order, compute RISC-V core based on the CV32E40P
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core-v-docs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
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core-v-sw
Main Repo for the OpenHW Group Software Task Group
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cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
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cv32e40s
4 stage, in-order, secure RISC-V core based on the CV32E40P
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core-v-mcu
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
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infra
Issues related to the OpenHW Group infra (GtHub, Mattermost, ...)
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openhwgroup.org
OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practi…
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pulp_soc
Forked from pulp-platform/pulp_soc -
core-v-cores
CORE-V Family of RISC-V Cores
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force-riscv
Instruction Set Generator initially contributed by Futurewei
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timer_unit
Forked from pulp-platform/timer_unit -
osdforum.org
The Open Source Developer Forum is a workshop that brings open source software and hardware (chips, boards and systems) developers together to collaborate and learn.
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riscv_vm
Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA board
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apb_interrupt_cntrl
Forked from pulp-platform/apb_interrupt_cntrlSmall and simple APB interrupt controller
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OpenHW-Admin-Tools
This is a private repo with tools and 'how-to' documentation for OpenHW Staff to use. We may make this repo public at some point.
