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Language: SystemVerilog
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pulp-platform / axi_node
AXI X-Bar
pulp-platform / fpnew
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
pulp-platform / axi_slice
Pipelines the AXI path with FIFOs
lowRISC / ariane-ethernet
open-source Ethenet media access controller for Ariane on Genesys-2
pulp-platform / axi_riscv_atomics
AXI Adapter(s) for RISC-V Atomic Operations
pulp-platform / fpga-support
IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs
pulp-platform / riscv-dbg
RISC-V Debug Support for our PULP RISC-V Cores
pulp-platform / fpu_div_sqrt_mvp
[UNRELEASED] FP div/sqrt unit for transprecision
pulp-platform / apb_timer
APB Timer Unit
pulp-platform / axi_mem_if
Simple single-port AXI memory interface
pulp-platform / axi2apb
pulp-platform / axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
openhwgroup / cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
pulp-platform / hwpe-stream
IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
pulp-platform / hwpe-ctrl
IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
lowRISC / opentitan
OpenTitan: Open source silicon root of trust
pulp-platform / udma_core
pulp-platform / axi_slice_dc
AXI Dual-Clock FIFO for clock domain crossings (CDC)

