YosysHQ / prjtrellis
Documenting the Lattice ECP5 bit-stream format.
| Jan | FEB | Mar |
| 06 | ||
| 2020 | 2021 | 2022 |

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Documenting the Lattice ECP5 bit-stream format.
RISC-V System on Chip Template Based on the picorv32 Processor
HDL libraries and projects
Verilog AXI components for FPGA implementation
Verilog configurable cache
IOb_SoC version of the Picorv32 RISC-V Verilog IP core
Repository for the SCALE-MAMBA MPC system
SERV - The SErial RISC-V CPU
RTL, Cmodel, and testbench for NVDLA
BaseJump STL: A Standard Template Library for SystemVerilog
Wraps the NVDLA project for Chipyard integration
Verilog behavioral description of various memories
handle bus interconnection
The Ultra-Low Power RISC-V Core
The USRP™ Hardware Driver Repository