SI-RISCV / e200_opensource
The Ultra-Low Power RISC Core
| Jan | FEB | Mar |
| 05 | ||
| 2020 | 2021 | 2022 |

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The Ultra-Low Power RISC Core
PicoRV32 - A Size-Optimized RISC-V CPU
Wraps the NVDLA project for Chipyard integration
RTL, Cmodel, and testbench for NVDLA
BaseJump STL: A Standard Template Library for SystemVerilog
HDL libraries and projects
Documenting the Lattice ECP5 bit-stream format.
Verilog AXI components for FPGA implementation
The USRP™ Hardware Driver Repository
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!