risc-v
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Jan 20, 2021 - Python
With Tock running on this board with virtual_uart sitting on top of USB, the Nano 33 BLE is a reasonably promising board to be a standard, well supported Tock board. Additionally, if the board turns out to not be great, the infrastructure which would make the Nano 33 BLE work well would apply to any other board that has the nRF52840 + USB combination.
- Make the bootloader and tockloader ex
About this question, here is a unified reply.
We need to see this place where one is the definition and load the configuration.
https://github.com/sipeed/MaixPy/blob/master/components/micropython/port/builtin_py/board.py
If you don't provide the configuration, you won't get the concrete variable.
If it is SIPEED published hardware, the appropriate configuration is provided here.
htt
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Jan 22, 2021 - C#
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Jan 18, 2021 - C++
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Jan 21, 2021 - C#
Try out svlint
I just found https://github.com/dalance/svlint and would be interested how it copes with the ibex code base.
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Jan 22, 2021 - C
I have just recently installed RARS as a replacement for RVS and there doesn't seem to be the ability to display the hex and decimal value at the same time.
If there is already a way to do this apologies for the issue.
This is discussed a bit more in #456.
Currently, to copy off files from the fs is to 1. mount, 2. chattr, 3. chmod/chown, 4. copy files off. However, this is destructive to the fs (since it changes permissions/users). Instead, there should be a less invasive way to copy off files that doesn't mess with the underlying fs so that people can copy the fs and use it somewhere else.
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Dec 11, 2020 - Forth
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May 3, 2020 - Verilog
Some RISC-V instructions perform writes to 2 destinations, either 2 register or register or program counter. In cases if the source of one sub-operation matches a destination of another one, the order of result output is important. The examples are jalr and instruction operating with CSRs:
riscv/riscv-tests#258
riscv/riscv-tests#263
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https://github.com/WebAssembly/bulk-memory-operations