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efabless / openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Verilog 245 67 Built by @agorararmard @ax3ghazy @tgingold @kassemmkk @mkkassem 1 stars today