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@sjtug @ACM-Class-2016
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Pinned

  1. EM-Compiler Public

    A compiler for Mx* (a C-and-Java-like language)

    Java 7 2

  2. RISC-V-CPU Public

    RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.

    Verilog 111 24

  3. Simulator of the five-stage pipeline to process MIPS instructions, written in C++

    C++ 7 3

  4. Lecture notes of Computer Architecture course, ACM Class, SJTU.

    TeX 8

  5. Python scripts to extend functions of personal WeChat accounts, using itchat. / 扩展个人微信账号功能的Python脚本,使用开源的WeChat的Python接口itchat。

    Python 21 11

33 contributions in the last year

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Contribution activity

October 2022

1 contribution in private repositories Oct 15