open-sdr

Repositories

• openwifi-hw

  FPGA/hardware design of openwifi

  linux fpga zynq hls verilog xilinx sdr
  Verilog AGPL-3.0 56 125 0 0 Updated Nov 6, 2020

• openofdm

  Forked from jhshi/openofdm

  Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
  Verilog Apache-2.0 62 22 0 0 Updated Nov 6, 2020

• openwifi

  open-source IEEE802.11/Wi-Fi baseband chip/FPGA design

  linux fpga zynq hls wifi verilog xilinx
  C AGPL-3.0 176 1,414 3 0 Updated Nov 6, 2020