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instruction-set-architecture

Here are 49 public repositories matching this topic...

hlorenzi / customasm

Star

💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/

rust processor-architecture vm bytecode compiler custom virtual-machine assembly asm assembler webassembly rust-lang customizable assembly-language microprocessor instruction-set-architecture machine-code bytecode-compiler instruction-set user-defined

Updated Sep 10, 2020
Rust

Maratyszcza / Opcodes

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Database of CPU Opcodes

x86-64 instructions x86 opcodes instruction-set-architecture

Updated Apr 24, 2018
Python

scarv / xcrypto

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XCrypto: a cryptographic ISE for RISC-V

open-source cryptography cpu crypto hardware riscv verilog research-project mit-license ise icarus-verilog hardware-acceleration formal-verification yosys instruction-set-architecture risc-v xcrypto

Updated Aug 17, 2020
Verilog

edanor / umesimd

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UME::SIMD A library for explicit simd vectorization.

Updated Jan 19, 2018
C++

zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial

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Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

cpu processor simd verilog alu adder instruction-set-architecture cadence-virtuoso multiplier verilog-project processor-design

Updated Oct 31, 2018
Verilog

dmjio / LC3

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💾 The LC3 virtual machine

haskell virtual-machine assembly opcodes lc3 instruction-set-architecture

Updated Jan 1, 2019
Haskell

sdasgup3 / parallel-processor-design

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Super scalar Processor design

processor-architecture bison flex processor assembler parallel-computing verilog forwarding bypassing pipeline-processor superscalar opcode verilog-hdl instruction-set-architecture instruction-set processor-simulator branch-prediction pipeline-cpu mnemonics instruction-level-parallelism

Updated Sep 7, 2014
Verilog

TomerAberbach / mano-simulator

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An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer.

java editor simulator architecture javafx assembler text-editor java8 java-8 javafx-application computer-architecture java-application mano instruction-set-architecture 16bit javafx-8 hardware-simulation mano-machine hardware-simulator mano-simulator

Updated Apr 29, 2020
Java

alirezakay / RISC-CPU

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A multi cycle RISC CPU (processor) like MIPS CPU in VHDL ( a hardware side code implementation )

processor-architecture cpu vhdl isa cpu-model instruction-set-architecture mips-processor vhdl-modules risc-processor vhdl-code cpu-architecture multi-cycle processor-design

Updated Jul 13, 2019
VHDL

scarv / scarv-cpu

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SCARV: a side-channel hardened RISC-V platform

open-source cryptography cpu crypto riscv verilog research-project mit-license ise formal-verification yosys instruction-set-architecture verilator riscv32 xcrypto

Updated Sep 11, 2020
Verilog

wisk / isabelle

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Instruction Set Architecture Description Format

instruction-set-architecture

Updated Aug 17, 2016
Python

Mograsim

Mograsim-Team / Mograsim

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Modular Graphical Simulator for Teaching Microprogramming

plugin emulator processor-architecture modular simulator tum amd eclipse processor assembler teaching graphical instruction-set-architecture microprogramming processor-simulator era am2900

Updated Sep 13, 2020
Java

suhassumukh / assembler

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Assembly Compiler

compiler assembler hexadecimal instruction-set-architecture

Updated Apr 12, 2017
C

GodTamIt / assembler

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A modular general 2-pass assembler written in Python.

parser modular assembly instructions assembler instruction-set-architecture

Updated Jan 27, 2018
Python

PrasithL / instruction-set-tutorial

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Tutorial on Instruction Set Architecture

sample tutorial instruction-set-architecture

Updated Feb 11, 2017
JavaScript

danilopeixoto / archer

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A simple instruction set architecture.

instruction-set-architecture

Updated Nov 16, 2018
C++

hardik22317 / Context-Switching

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Multi-Threaded Simulation of Process Switching in Operating System.

c multi-threading operating-system threading instruction-set-architecture process-scheduler process-simulator

Updated Jul 16, 2018
C

jmcph4 / cpu

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My attempt at a CPU simulator

c simulator cpu simulation processor assembly architecture instructions isa instruction-set-architecture machine-code

Updated Dec 16, 2016
C

yanalex981 / 6502vm

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6502 virtual machine written in C

c virtual-machine 6502 instruction-set-architecture

Updated Mar 14, 2017
C

levindoneto / MIPS

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Microprocessor without Interlocked Pipeline Stages with the extra JR, DIV and MFLO instructions implemented.

processor-architecture mips pipeline-processor instruction-set-architecture multicycle-processor monocycle-processor

Updated Oct 7, 2016

zsisco / yaye

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yaye is Yet Another y86 Emulator

emulator instruction-set-architecture

Updated Jan 26, 2017
C

Sacusa / MoCha

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A pedagogical processor on FPGA, developed at NIIT University.

cpu fpga processor vhdl assembler assembly-language microprocessor educational synthesis bootloader computer-architecture cycle-accurate vlsi stepper-motor-driver spi-flash instruction-set-architecture architectural-simulation microarchitecture bit-banging

Updated Oct 1, 2018
VHDL

mograsim-documentation

Mograsim-Team / mograsim-documentation

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Sources of the Mograsim Documentation and Website

plugin emulator processor-architecture modular simulator tum amd eclipse processor assembler teaching graphical instruction-set-architecture microprogramming processor-simulator era am2900 mograsim

Updated Sep 11, 2020

8shubham / Smart-Home-Controller

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A real time computing machine

c simulation assembler computer-architecture instruction-set-architecture microarchitecture

Updated Aug 18, 2017
C

VenkatKS / CHIP8

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Full graphical instruction-level emulator for the CHIP-8 Instruction Set Architecture

c emulator opengl chip-8 terminal-based instruction-set-architecture instruction-level

Updated Jun 8, 2017
C

nhays89 / PC-sim

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c assembler & data path simulator implementing the LC-2200 ISA.

c debugger gtk assembler instruction-set-architecture register-machine lc-2200

Updated Feb 5, 2018
C

Roninkoi / RAKIAC

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RAKIAC computer ISA with assembler and simulator

cpu assembler instruction-set-architecture processor-simulator

Updated Feb 2, 2020
Fortran

sid-137 / RNBIP_Pipelined-Microprocessor

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Redesigned the RNBIP single-bus architecture to implement a 3 stage instruction-level pipeline.

fpga architecture microprocessor academic-project instruction-set-architecture instruction-level-parallelism

Updated Apr 26, 2020
Verilog

Fhoughton / ToyVM

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A small toy VM and assembler written in python as a learning exercise. Has 3 registers, with storage, maths and printing.

virtual-machine assembler instruction-set-architecture

Updated Jan 3, 2020
Python

mariusdahl27 / aura

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The definition of the AVRA computer architecture

aura computer-architecture instruction-set-architecture

Updated Aug 4, 2020

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