#
xilinx
Here are 348 public repositories matching this topic...
litghost
commented
Oct 29, 2020
Once #1475 is complete, populate part data for all parts that fabric documentation exists for. #1475 should be done first to avoid duplicating all of the fabric data repeatedly.
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
-
Updated
Jul 7, 2020 - SystemVerilog
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
python
infrastructure
asic
fpga
simulation
vhdl
verification
xilinx
synthesis
regression-testing
altera
hardware-designs
lattice
hardware-libraries
poc-library
vlsi
testbenches
hardware-modules
osvvm
uvvm
vunit
-
Updated
Sep 26, 2020 - VHDL
HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs
deep-neural-networks
inference
dnn
xilinx
alexnet
googlenet
embedded-vision
xilinx-ultrascale-mpsocs
-
Updated
Jul 9, 2019 - C++
A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.
fpga
driver
xilinx
zedboard
axi-dma
linux-driver
axi-vdma
dma-driver
xilinx-axi-dma
xilinx-axi-vdma
userspace-dma
fpga-dma
-
Updated
Feb 12, 2020 - C
An abstraction library for interfacing EDA tools
fpga
simulation
vhdl
eda
verilog
xilinx
synthesis
vivado
altera
systemverilog
icestorm
lattice
icarus-verilog
modelsim
ghdl
yosys
verilator
riviera-pro
fossi
spyglass
-
Updated
Nov 5, 2020 - Python
Must-have verilog systemverilog modules
generator
fpga
clock
encoder
delay
tcl
verilog
debounce
xilinx
uart
altera
multichannel
pulse
fifo
modelsim
lifo
spi-master
spi-slave
uart-transmitter
uart-receiver
-
Updated
Nov 3, 2020 - Verilog
Bus bridges and other odds and ends
-
Updated
Oct 22, 2020 - Verilog
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
cmake
asic
fpga
cpp
verification
rtl
verilog
xilinx
vivado
systemverilog
systemc
unit-tests
hdl
modelsim
uvm
verilator
quartus
testing-rtl
-
Updated
Nov 25, 2019 - SystemVerilog
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
linux
iot
fpga
zynq
tensorflow
assembly
vhdl
embedded-systems
internet-of-things
hardware-architectures
verilog
xilinx
vivado
tensor
hardware-designs
hardware-acceleration
fpga-accelerator
hardware-description-language
ip-core
tpu
-
Updated
Jan 5, 2019 - VHDL
Build Customized FPGA Implementations for Vivado
-
Updated
Nov 6, 2020 - Java
32-bit Superscalar RISC-V CPU
linux
asic
cpu
fpga
verilog
xilinx
superscalar
in-order
risc-v
branch-prediction
coremark
rv32i
verilator
riscv-linux
rv32im
artix-7
pipelined-processors
-
Updated
Sep 21, 2020 - Verilog
A collection of extensions for Vivado HLS and Intel FPGA OpenCL to improve developer quality of life.
-
Updated
Sep 14, 2020 - C++
Repurposing existing HDL tools to help writing better code
python
vim
language-server
vhdl
issue-tracker
standalone
verilog
xilinx
syntax-checker
systemverilog
trademarks
hdl
modelsim
questasim
ghdl
xilinx-vivado
lsp-server
coc-nvim
vim-ale
vivado-simulator
mentor-msim
hdl-checker
emacs-lsp
-
Updated
Nov 5, 2020 - Python
Simple, zero-copy DMA to/from userspace.
-
Updated
Sep 18, 2017 - C
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
productivity
pathogen
vhdl
vim-plugins
verilog
xilinx
syntastic
syntax-checker
altera
systemverilog
trademarks
vundle
modelsim
hdlcc-issue-tracker
vimhdl-issue-tracker
vim-hdl
registered-trademarks
-
Updated
Oct 28, 2019 - Python
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
simulator
encoder
decoder
priority
isbn
verilog
xilinx
testbenches
multiplexer
comparator
adder
system-verilog
xilinx-vivado
highest
half-adder
traffic-light-controller
full-adder
ripple-adder
look-ahead-adder
-
Updated
Oct 2, 2019 - Verilog
Improve this page
Add a description, image, and links to the xilinx topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the xilinx topic, visit your repo's landing page and select "manage topics."
If you speak another language, I would appreciate your help in translating the
README.md.For tables, checklists, or other data that might change, please indicate that that information is in the main README. Otherwise every change to the main README will need to be replicated to the other READMEs.
^ I've tried to do this a bit in the French README. The only thing you need to replicate when