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mips
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Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings.
security
arm
framework
mips
x86-64
ethereum
reverse-engineering
disassembler
webassembly
riscv
x86
arm64
sparc
m68k
powerpc
systemz
bpf
m0s65xx
m680x
tms320c64x
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Nov 15, 2020 - C
Plasma is an interactive disassembler for x86/ARM/MIPS. It can generates indented pseudo-code with colored syntax.
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May 16, 2020 - Python
Binary Analysis Platform
emulator
security
arm
mips
static-analysis
ocaml
reverse-engineering
disassembler
symbolic-execution
bap
x86
dynamic-analysis
binary-analysis
instruction-semantics
program-analysis
taint-analysis
powerpc
program-verification
lifter
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Nov 13, 2020 - OCaml
The OpenSource Disassembler
linux
esp8266
arm
cplusplus
cross-platform
mips
esp32
reverse-engineering
esp
disassembler
capstone
qt5
ida
ida-pro
dalvik
binary-analysis
espressif
xtensa
dex
idapro
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Nov 9, 2020 - C++
Simple C compiler
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Oct 6, 2020 - C
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
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Jul 7, 2020 - SystemVerilog
C--compiler which implements LL(1)\LR(0)\SLR\LR(1) and semantic analysis and MIPS generate
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Nov 30, 2019 - Python
Simple and lightweight source-based multi-platform Linux distribution with musl libc.
linux
fast
distribution
arm
privacy
cross-platform
simple
mips
linux-distribution
x86
cross-compiler
safe
musl
musl-libc
powerpc
compact
risc-v
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Nov 15, 2020 - C
Cross complie shadowsocks for UBNT devices based on mipsel or mips64
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Mar 22, 2020 - Shell
A curated list of Nintendo 64 development resources including toolchains, documentation, emulators, and more
c
rust
gamedev
documentation
awesome
nintendo
tools
mips
asm
game-development
assembler
development-kit
resources
cartridge
mips-assembly
awesome-list
rom
n64
nintendo-64
assembly-programming
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Nov 12, 2020 - Python
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Some RISC-V instructions perform writes to 2 destinations, either 2 register or register or program counter. In cases if the source of one sub-operation matches a destination of another one, the order of result output is important. The examples are
jalrand instruction operating with CSRs:riscv/riscv-tests#258
riscv/riscv-tests#263
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