pulp-platform

Repositories

• pulp

  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
  SystemVerilog 39 132 7 1 Updated Oct 22, 2020

• pulp_cluster

  The multi-core cluster of a PULP system.
  SystemVerilog 3 2 0 2 Updated Oct 22, 2020

• pulp-runtime

  Simple runtime for Pulp platforms
  C 3 0 0 0 Updated Oct 21, 2020

• pulp-dsp
  C Apache-2.0 16 10 1 1 Updated Oct 20, 2020

• hwpe-stream

  IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
  SystemVerilog 8 4 1 1 Updated Oct 19, 2020

• axi

  AXI4 and AXI4-Lite synthesizable modules and verification infrastructure

  asic fpga hardware rtl systemverilog axi network-on-chip
  SystemVerilog 55 175 11 11 Updated Oct 19, 2020

• riscv-dbg

  RISC-V Debug Support for our PULP Cores
  SystemVerilog 29 38 15 11 Updated Oct 19, 2020

• hal
  C Apache-2.0 4 4 1 2 Updated Oct 18, 2020

• fpnew

  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  SystemVerilog 27 79 4 (1 issue needs help) 6 Updated Oct 15, 2020

• pulpissimo

  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
  SystemVerilog 66 127 52 2 Updated Oct 9, 2020

• common_cells

  Common SV components
  SystemVerilog 38 60 15 3 Updated Oct 6, 2020

• pulp-runtime-examples

  Examples for pulp-runtime
  C 1 0 0 0 Updated Oct 6, 2020

• fpu_div_sqrt_mvp

  [UNRELEASED] FP div/sqrt unit for transprecision
  SystemVerilog 4 4 1 1 Updated Oct 5, 2020

• pulp_soc
  SystemVerilog 12 11 0 0 Updated Oct 2, 2020

• register_interface

  Generic Register Interface (contains various adatpers)
  SystemVerilog 5 2 0 0 Updated Sep 28, 2020

• hwpe-ctrl

  IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
  SystemVerilog 8 2 2 2 Updated Sep 28, 2020

• q-eegnet_wolf
  C Apache-2.0 0 0 0 0 Updated Sep 23, 2020

• pulp-nn
  C Apache-2.0 8 29 0 0 Updated Sep 15, 2020

• mchan
  SystemVerilog 3 0 1 0 Updated Sep 15, 2020

• fpu_interco
  SystemVerilog 1 0 0 1 Updated Aug 28, 2020

• pulp-riscv-gnu-toolchain
  C 19 19 24 0 Updated Aug 26, 2020

• pulp-riscv-binutils-gdb
  C 11 0 2 3 Updated Aug 26, 2020

• pulp-riscv-gcc
  C 9 3 1 0 Updated Aug 26, 2020

• mempool
  Makefile Apache-2.0 0 0 0 0 Updated Aug 24, 2020

• cluster_interconnect
  SystemVerilog 5 2 0 2 Updated Aug 21, 2020

• hci_interconnect

  Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
  SystemVerilog 2 0 0 0 Updated Aug 18, 2020

• dory

  A tool to deploy Deep Neural Networks on PULP-based SoC's
  Python Apache-2.0 1 6 0 0 Updated Aug 18, 2020

• dory_examples
  C Apache-2.0 0 1 0 0 Updated Aug 10, 2020

• pulp-sdk
  Shell Apache-2.0 33 39 6 0 Updated Aug 7, 2020

• pulp-configs

  Contains JSON description of pulp configurations
  Python 5 0 0 0 Updated Aug 3, 2020