mips-processor

A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

5-stage pipelined 32-bit MIPS microprocessor in Verilog

It's all coming back into focus!

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

A 5-stage pipelined mips32 processor

An ELF parser, which calculates stack usage for embedded mips microcontroller, especially for Microchip's XC32 compiler

A low power, high performance 32-bit, 5-cycle MIPS core that implements a subset of instructions.

DEPRECATED!!! An (almost) fully functional theme engine for MARS.

A pipelined implementation of a MIPS processor that was optimized to use data forwarding, caching and branch prediction.

Modification of the MARS program originally written by Kenneth Vollmar and Pete Sanderson at Missouri State University.

Core part of a mini processor simulator called MySPIM using the C language on a Unix/Linux platform. MySPIM demonstrates some functions of the MIPS processor as well as the principle of separating the data-path from the control signals of the MIPS processor. The MySPIM simulator reads in a file containing MIPS machine code (in a specified the format) and simulates what MIPS does cycle-by-cycle (single-cycle data path).

MIPS simulator written in Go

💻 MIPS Pipeline Processor simulator

Heo is a cycle-accurate multicore architectural simulator written in Go.

simulator of a MIPS processor in C

A MIPS processor with Cache and Advanced Branch Predictor written in SystemVerilog

🔮 A 16-bit MIPS Processor Implementation in Verilog HDL

Mips Multi-Cycle, Computer Architecture course, University of Tehran

Solution for the assignment in Digital Design and Computer Architecture course including test benches running faster than official nightly tests.

the tiniest MIPS R4300i assembler and disassembler

A 32-bit MIPS processor developed in Verilog based on pipeline

A 2-stage Pipelined MIPS Processor in Verilog

🐢 用 Verilog 实现的单周期 MIPS 指令集的 CPU，并用它来计算斐波那契数。

Simulation of Designs of Basic Computer & Processor Architecture(4-bit MIPS CPU, Floating Point Adder) in Logisim as assignments of Computer Architecture Sessional course of CSE 306 of CSE, BUET

Simplified implementation of MIPS pipelined processor

Mips Single-Cycle, Computer Architecture course, University of Tehran

Practica 2 de Arquitectura computacional

🔮 A 32-bit MIPS Processor Implementation in Verilog HDL