Portable file system cache diagnostics and control

A simple guide to x86 architecture, assembly, memory management, paging, segmentation, SMM, BIOS....

Incompatible Timesharing System

This is a series of small articles / tutorials based around virtual memory. The goal is to learn some CS basics, but in a different and more practical way.

My notes while studying Windows internals

cross platform library to manipulate and extract information of memory regions

Provides Rust interface to get current memory mappings for a given process

Peek/Poke like it's 1979 - Multi-Platform memory reading/writing

hello world operating system

计算机组成原理中虚拟存储器的实现（A Virtual Memory Implementation In Computer Organization）.

模拟操作系统段页式虚拟内存管理

Library to handle hexadecimal record files

Virtual memory (VM) manager for 26-bit ARMv3 and ARMv4 based computers running Acorn’s RISC OS

In this lab, you are required to complete a virtual memory implementation, including how to get a physical frame for a virtual page from the IPT if it exists there, how to put a physical frame/virtual page entry into TLB, and how to implement a least recently used page replacement algorithm. A software-managed TLB is implemented in Nachos. There is one TLB per machine. There is also an IPT which maps physical frames to virtual pages. Basically, the translation process first examines the TLB to see if there is a match. If so, the matching entry in the TLB will be used for address translation. If there is a miss, the IPT will be looked up. If a matching entry is found in the IPT, the entry will be used to update the TLB. A miss in the IPT means that the page will have to be loaded from disk, and a page in and page out will be performed. To decide which page to page out, a page replacement policy is used, for example, a least recently used algorithm which will be explained late on. During each lookup process, you need to perform some checking in order to make sure that you are looking up the correct entry and that the entry is valid. In order to check whether you are referencing the correct entries from the TLB, you have to check the valid bit. The TLB will get updated when an exception is raised and the required page entry isn't in it. In this case, a new entry needs to be inserted into the TLB. The new entry will be inserted into an invalid entry in the TLB or replace an existing entry if it is full. Since the TLB is small, the replacement policy for the TLB is simply FIFO. When there is a context switch between processes, e.g. the main process executing a child process, the entries in the TLB will be cleared by setting all entries to invalid. The IPT is simply implemented using an array, represented by the memoryTable (a mapping of what pages are in memory and their properties). There is one entry for each of the physical frame, and each entry contains the corresponding process id, virtual page number, and the last used field that records the tick value when the page was last accessed. The least recently used algorithms works by iterating through the memoryTable, from the beginning, to look for the entry that has been least recently used. If there is an entry that is not valid (i.e., its process is dead), the algorithm will return the index of this invalid entry. Otherwise, the algorithm will return the index of the least recently used entry (that is, the entry with the smallest last used field).

Block storage framework and a collection of projects built on top of this high-performance subsystem.

unsafe hacky memory accessor written in go. $ go get -v github.com/nanitefactory/memory

Pash Assembly interpreter written in C++

A 64-bit cooperative multi-tasking toy operating system in C

A basic operating system for x86 architecture(64 bit) with TARFS filesystem. Supports fork(), cow(), paging, virtual memory/ring3 user process and syscall using INT $80. Able to run a shell and binaries: ls, cat, echo, kill, ps,sleep

Eyeball Allocation Table

The assignment on Virtual Memory in OS332C

Basic Operating System for Time Sharing Kernel, ISR, System Calls, Device Drivers, Process Scheduling, Memory Management, Paging, Synchronization and developing kernel services for supporting embedded systems.

Translates logical address to physical address for a virtual address space of 2^16 (65,536) bytes.

Multithreaded usermode virtual memory manager state machine

OS implementation for Caltech CS124

Управление виртуальной памятью.

Simulation and data analysis for 4 different page replacement algorithms

The goal of this project is to implement a simulator for a virtual memory manager.