pulp-platform

Repositories

• common_cells

  Common SV components
  SystemVerilog 37 60 15 3 Updated Sep 8, 2020

• pulpissimo

  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
  SystemVerilog 62 122 44 1 Updated Sep 3, 2020

• pulp_soc
  SystemVerilog 12 10 0 0 Updated Sep 3, 2020

• fpnew

  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  SystemVerilog 25 73 4 (1 issue needs help) 6 Updated Sep 2, 2020

• fpu_interco
  SystemVerilog 0 0 0 1 Updated Aug 28, 2020

• pulp-riscv-gnu-toolchain
  C 19 17 21 0 Updated Aug 26, 2020

• pulp-riscv-binutils-gdb
  C 10 0 2 3 Updated Aug 26, 2020

• pulp-riscv-gcc
  C 8 3 1 0 Updated Aug 26, 2020

• register_interface

  Generic Register Interface (contains various adatpers)
  SystemVerilog 4 2 0 0 Updated Aug 25, 2020

• mempool
  Makefile Apache-2.0 0 0 0 0 Updated Aug 24, 2020

• cluster_interconnect
  SystemVerilog 5 2 0 2 Updated Aug 21, 2020

• hwpe-ctrl

  IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
  SystemVerilog 8 2 2 2 Updated Aug 18, 2020

• hwpe-stream

  IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
  SystemVerilog 8 4 1 1 Updated Aug 18, 2020

• hci_interconnect

  Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
  SystemVerilog 2 0 0 0 Updated Aug 18, 2020

• dory

  A tool to deploy Deep Neural Networks on PULP-based SoC's
  Python Apache-2.0 1 5 0 0 Updated Aug 18, 2020

• pulp-nn
  C Apache-2.0 7 27 0 0 Updated Aug 17, 2020

• dory_examples
  C Apache-2.0 0 0 0 0 Updated Aug 10, 2020

• pulp-dsp
  C Apache-2.0 15 10 2 1 Updated Aug 10, 2020

• axi

  AXI4 and AXI4-Lite synthesizable modules and verification infrastructure

  asic fpga hardware rtl systemverilog axi network-on-chip
  SystemVerilog 47 157 10 10 Updated Aug 7, 2020

• pulp-sdk
  Shell Apache-2.0 32 38 6 0 Updated Aug 7, 2020

• pulp

  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
  SystemVerilog 38 124 7 0 Updated Aug 6, 2020

• pulp_cluster

  The multi-core cluster of a PULP system.
  SystemVerilog 2 2 0 2 Updated Aug 6, 2020

• riscv-dbg

  RISC-V Debug Support for our PULP Cores
  SystemVerilog 27 30 9 4 Updated Aug 4, 2020

• pulp-configs

  Contains JSON description of pulp configurations
  Python 5 0 0 0 Updated Aug 3, 2020

• mchan
  SystemVerilog 1 0 0 0 Updated Aug 3, 2020

• plptest

  Script for automating tests
  Python 1 0 0 0 Updated Aug 3, 2020

• udma_i2s
  SystemVerilog 3 0 0 2 Updated Jul 30, 2020

• pulp-rt
  C Apache-2.0 5 8 0 1 Updated Jul 30, 2020

• hier-icache
  SystemVerilog 2 5 0 0 Updated Jul 28, 2020

• scm
  SystemVerilog 1 0 0 0 Updated Jul 28, 2020