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lattice
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attacking RSA via lattice reductions (LLL)
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Jul 18, 2017 - TeX
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
python
infrastructure
asic
fpga
simulation
vhdl
verification
xilinx
synthesis
regression-testing
altera
hardware-designs
lattice
hardware-libraries
poc-library
vlsi
testbenches
hardware-modules
osvvm
uvvm
vunit
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Sep 26, 2020 - VHDL
An abstraction library for interfacing EDA tools
fpga
simulation
vhdl
eda
verilog
xilinx
synthesis
vivado
altera
systemverilog
icestorm
lattice
icarus-verilog
modelsim
ghdl
yosys
verilator
riviera-pro
fossi
spyglass
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Sep 29, 2020 - Python
ASR with PyTorch
python
decoder
speech
pytorch
speech-recognition
densenet
resnet
kaldi
lattice
transcription
dictation
asr
pyro
ctc
deepspeech
capsule-network
lvcsr
pytorch-binding
kaldi-decoder
ss-vae
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Mar 10, 2019 - Python
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Sep 12, 2020 - HTML
Low-cost ECP5 FPGA development board
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Sep 1, 2020 - Python
Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom
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May 21, 2020 - VHDL
A Python Library for Energy Profile and Abstract Grid(2D/3D) plotting
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Dec 12, 2018 - Python
A General-Purpose Tool for Formal Concept Analysis
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Oct 1, 2020 - Clojure
WP6 of the SAFEcrypto project - a suite of lattice-based cryptographic schemes
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Jan 20, 2020 - C
Markov chain Monte Carlo solver for lattice spin systems implemented by Julialang
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Jun 26, 2020 - Julia
Lattice iCE40: development platform for PlatformIO
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Sep 3, 2020 - Python
PyQt based GUI tool which allows to visualize, design and export the lattice graph models.
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May 15, 2017 - Python
First SDR platform for IoT networks
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Jun 27, 2020 - C
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Vendor tools dram tests were not enabled until #1234 got merged.
With SymbiFlow/symbiflow-arch-defs#1268 I have temporarily disabled the vivado_targets, to let CI go green (as it has been red for too long now).
This issue is to keep track of the problem with DRAM evaluated on vendor tools with fasm2bels.