SpinalHDL

Repositories

• VexRiscv

  A FPGA friendly 32 bit RISC-V CPU implementation

  cpu fpga vhdl riscv verilog soc spinalhdl
  Assembly MIT 141 865 37 4 Updated Sep 7, 2020

• SpinalHDL

  Scala based HDL

  scala fpga vhdl rtl verilog
  Scala 106 568 33 9 Updated Sep 7, 2020

• SaxonSoc

  SoC based on VexRiscv and ICE40 UP5K

  riscv rtl soc
  Scala MIT 11 54 5 0 Updated Sep 6, 2020

• SpinalDoc-RTD

  The sources of the online SpinalHDL doc

  documentation spinalhdl
  Python 13 7 5 0 Updated Sep 4, 2020

• Spinal-bootcamp

  Forked from jijingg/Spinal-bootcamp

  SpinalHDL-tutorial based on Jupyter Notebook
  Jupyter Notebook 8 3 0 0 Updated Sep 2, 2020

• openocd_riscv

  Forked from Dolu1990/openocd_riscv

  Spen's Official OpenOCD Mirror
  C GPL-2.0 309 15 3 0 Updated Sep 1, 2020

• u-boot

  Forked from u-boot/u-boot

  "Das U-Boot" Source Tree
  C 1,555 0 0 0 Updated Sep 1, 2020

• buildroot

  Forked from buildroot/buildroot

  Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at http://git.buildroot.net/buildroot/. Do not open issues or file pull requests here.
  Makefile 1,167 0 0 0 Updated Sep 1, 2020

• opensbi

  Forked from riscv/opensbi

  RISC-V Open Source Supervisor Binary Interface
  C 94 0 0 0 Updated Sep 1, 2020

• SpinalWorkshop

  Labs to learn SpinalHDL
  Scala 10 43 4 0 Updated Aug 2, 2020

• embench-iot

  Forked from embench/embench-iot

  The main Embench repository
  C GPL-3.0 38 0 0 0 Updated Jul 8, 2020

• linux
  C 1 0 0 1 Updated Jun 29, 2020

• docker
  Dockerfile 3 0 0 1 Updated Jun 18, 2020

• CocotbLib
  Python MIT 4 7 1 0 Updated Jun 17, 2020

• SpinalTemplateMill

  Forked from typingArtist/SpinalTemplateMill

  A simple SpinalHDL demo project based on Mill
  Scala 1 0 0 0 Updated Jun 12, 2020

• SpinalCrypto

  SpinalHDL - Cryptography libraries

  cryptography scala crypto fpga aes vhdl md5
  Scala MIT 7 12 0 0 Updated Jun 8, 2020

• SpinalDoc

  SpinalHDL documentation assets (pictures, slides, ...)
  HTML 9 15 1 0 Updated May 4, 2020

• SpinalTemplateSbt

  A basic SpinalHDL project
  Scala 9 15 0 0 Updated Apr 21, 2020

• SpinalTemplateSbtDependencies

  An SpinalHDL project example which use VexRiscv git as a dependency
  Scala 0 1 0 0 Updated Mar 9, 2020

• SpinalTemplateGradle

  A basic SpinalHDL project, configured with Gradle instead of SBT
  Scala 0 0 0 0 Updated Dec 15, 2019

• sd_device

  Forked from fusesoc/sd_device

  SD device emulator from ProjectVault
  Verilog Apache-2.0 2 0 0 0 Updated Dec 3, 2019

• zephyr

  Forked from zephyrproject-rtos/zephyr

  Primary GIT Repository for the Zephyr Project
  C Apache-2.0 2,199 0 0 0 Updated Apr 21, 2019

• VexRiscvRegressionData

  Used to store heavy data required to run full VexRiscv regressions
  Assembly 4 0 0 0 Updated Apr 21, 2019

• coremark

  Forked from eembc/coremark

  CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).
  C 105 0 0 0 Updated Apr 21, 2019

• VexRiscvSoftcoreContest2018
  Verilog Apache-2.0 13 50 0 0 Updated Dec 16, 2018

• riscv-compliance

  Forked from riscv/riscv-compliance
  Assembly 77 0 0 0 Updated Nov 18, 2018

• VexRiscvSocSoftware
  C 9 8 0 0 Updated Sep 20, 2018

• riscv-formal

  Forked from SymbioticEDA/riscv-formal

  RISC-V Formal Verification Framework
  Verilog ISC 47 3 0 0 Updated Aug 28, 2018

• SpinalBaseProject-OLD-
  Scala 4 11 0 0 Updated Dec 18, 2017

• cocotb

  Forked from cocotb/cocotb

  Coroutine Co-simulation Test Bench
  Python 238 0 0 0 Updated Sep 5, 2017