The Wayback Machine - https://web.archive.org/web/20200708201414/https://github.com/topics/jspec

#

jspec

Here is 1 public repository matching this topic...

Juniper / open-register-design-tool

Star

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

asic fpga eda systemverilog uvm registers systemrdl jspec register-descriptions systemrdl-compiler

Updated Oct 20, 2019
Verilog

Improve this page

Add a description, image, and links to the jspec topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the jspec topic, visit your repo's landing page and select "manage topics."

You can’t perform that action at this time.