If this is not the case a page fault should be generated. Right now we generate an instruction access fault.

https://github.com/pulp-platform/ariane/blob/ad70ce1f30dad539e5a365ffe71a02aaf20b397e/src/load_store_unit.sv#L339

Author Name: Driss Hafdi
Original Redmine Issue: 1624 from https://www.veripool.org

If a variable of the wrong witdth is passed in as a parameter, verilator prints out in its warning the parameter definition location, whereas it would be more helpful to get the reference of the value that was passed in, particularly with bigger design with multiple levels of hierarchy. Here is a

Here is a simple example for Vivado.

https://github.com/SymbiFlow/fpga-tool-perf/blob/f8438d0447ae808fd1434073b037fa30b274c423/fpgaperf.py#L444-L506

    def vivado_resources(self):
        report_path = self.out_dir + "/" + self.project_name + ".runs/impl_1/top_utilization_placed.rpt"
        with open(report_path, 'r') as fp:
            report_data = fp.read()
            repo

Verilator should only run on Verilog-HDL with proper Verilog file extensions.

maybe a

verilog.lint.include : [".sv", ".v"] //Verilog HDL/SystemVerilog configuration setting