Roa Logic BV

Repositories

• rltheme

  Roa Logic Theme for GitHub Pages
  SCSS 0 0 0 0 Updated Nov 23, 2020

• ahb3lite_interconnect

  AHB3-Lite Interconnect

  switch interconnect amba ahb3-lite
  SystemVerilog 16 36 1 0 Updated Nov 20, 2020

• roalogic.github.io

  Roa Logic GitHub Pages Site (Top Level)

  asic fpga riscv ip apb roalogic ahb
  SCSS 3 2 0 0 Updated Nov 20, 2020

• RV12

  RISC-V CPU Core

  cpu risc-v 32-bit 64bit
  SystemVerilog 34 164 5 0 Updated Nov 11, 2020

• plic

  Platform Level Interrupt Controller
  SystemVerilog 8 12 2 0 Updated Nov 2, 2020

• ahb3lite_apb_bridge

  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.

  amba apb ahb3-lite apb-bridge
  SystemVerilog 9 15 0 1 Updated Aug 31, 2020

• apb4_gpio

  General Purpose IO with APB4 interface

  gpio amba apb
  SystemVerilog 4 2 0 0 Updated May 26, 2020

• ahb3lite_memory

  Multi-Technology RAM with AHB3Lite interface

  amba ahb3-lite ahb3lite-memory
  SystemVerilog 7 10 0 0 Updated Sep 6, 2019

• vi_systemverilog_syntax

  VIM Syntax file for SystemVerilog

  syntax-highlighting vim systemverilog vim-syntax vi-systemverilog-syntax
  Vim script 2 5 0 0 Updated Aug 16, 2019

• ahb3lite_pkg

  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  SystemVerilog 5 9 0 0 Updated Aug 16, 2019

• Hamming-ECC

  Hamming ECC Encoder and Decoder to protect memories
  SystemVerilog 16 6 0 0 Updated Jun 11, 2019

• ahb3lite_timer

  RISC-V compliant Timer IP

  timer risc-v ahb3-lite
  SystemVerilog 5 7 0 0 Updated Jun 11, 2019

• memory

  Generic memory implementations
  SystemVerilog 9 4 1 0 Updated Aug 23, 2018

• vga_lcd

  VGA LCD Core (OpenCores)
  Verilog BSD-2-Clause 2 4 1 0 Updated May 22, 2018

• adv_dbg_if

  Universal Advanced JTAG Debug Interface
  SystemVerilog 7 13 0 0 Updated Dec 12, 2017

• apb4_mux

  APB4 Multiplexor

  apb
  SystemVerilog 1 3 0 0 Updated Nov 1, 2017

• riscv-isa-manual

  Forked from riscv/riscv-isa-manual

  RISC-V Instruction Set Manual
  TeX CC-BY-4.0 279 0 0 0 Updated Sep 27, 2017

• riscv_gnu_eclipse

  Eclipse Plugin for RISC-V GNU Toolchain

  toolchain eclipse risc-v riscv-gnu-eclipse
  Java 4 3 0 0 Updated Jun 27, 2017

• universal_jtag_tap

  Universal JTAG TAP Controller
  SystemVerilog 2 4 0 0 Updated May 9, 2017

• rv_soc

  Roa Logic RISC-V SoC
  0 1 0 0 Updated May 5, 2017

• adv_jtag_bridge
  C 3 2 0 0 Updated Apr 22, 2016