This is not intended to work. Why would you need it?

I want to use the same parameter inside my test class and as the name of the test case.

Do you instantiate the test class within the TEST_CASE block? In that case we might be able to add a current_test_case which returns a string.

I do not want any dynamic code in the test case definition itself since we by design want to statically know all test case names without elaborating or running Verilog code.

Yes, I instantiate test class inside TEST_CASE block.

design want to statically know all test case names without elaborating or running Verilog code.

Why is it good? What are advantages?

Elaborating or running Verilog code which would be unnecessarily complexity which is always something to avoid. Maybe in your simple case a static check could suffice but in the general case it would not. It is a desirable property of a test system that all test names are known prior to executing the actual code such that listing all test cases using for example --list argument does not require running any code to "discover" what where the tests.

Modelsim allows setting parameters from do file. For example, I can define a list of tests in run.py file and pass it to testbench and to VUnit. It will be defined outside SystemVerilog code. Does it solve this problem?

It would be good if your documentation mentions about the restriction in the naming TEST_CASE.