因为要使用rtt+emwin，在emwin532版本里，GUI_X_OS.c是和os的接口，在rtconfig.h里打开#define RT_USING_CMSIS_OS后，编译出了几条错误，如下
cmsis_rtthread.c
Error[Pe167]: argument of type "os_pthread" is incompatible with parameter of type "void (*)(void *)" \RTThread\rt-thread-v2.1.x\components\CMSIS\RTOS\cmsis_rtthread.c 33
Warning[Pe188]: enumerated type mixed with another type \RTThread\rt-thread-v2.1.x\components\CMSIS\RTOS\cm

Env:

• python 3.8
• capstone 4.0.1
• ubuntu 18.04 (WSL)

Repro:

import capstone
md = capstone.Cs(capstone.CS_ARCH_X86, capstone.CS_MODE_32)
md.detail = True

# case 1
# expected: fstcw  WORD PTR [ebp-0x4] (based on Objdump disassembly which round-trips with GNU as)
for insn in md.disasm(b"\x9B\xD9\x7D\xFC", 0):
    print(insn.address, insn.mnemonic, insn.op_str)

print(

COPYING and README claim this is GPL, but it doesn't specify which version exactly? It looks like GPLv2, the question is: "GPLv2 only" or "GPLv2 or later"?
The current uc.c only contains a copyright where it's unclear wether that file also belongs to GPL'd code.
The source files or README should contain [the license text as per COPYING file](https://github.com/unicorn-engine/unicorn/blob/master/CO

xargo CI is failing with a strange ICE:

thread 'rustc' panicked at 'failed to lookup `SourceFile` in new context', src/librustc_middle/ty/query/on_disk_cache.rs:456:17

note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace

error: internal compiler error: unexpected panic

note: the compiler unexpect

Just a quick question, do you think we should add a flag to keystone that will log all assemble attempts and their results? This could help for detecting inconsistencies, however it might be out of the scope for the project.

Our documentation site is always lagging behind as updating the docs is a non-trivial task that has to be automated. Setting up the Travis job for building wouldn't be trivial (we probably won't fit into the time constraints), but we can use GitHub actions and host a documentation builder on one of our servers. We shall update both bap documentation and Primus Lisp docs.

Please create the wiki page, and move all main content to it. Then link main sections to it to keep the front page clean and allow quick navigation.

Some RISC-V instructions perform writes to 2 destinations, either 2 register or register or program counter. In cases if the source of one sub-operation matches a destination of another one, the order of result output is important. The examples are jalr and instruction operating with CSRs:

riscv/riscv-tests#258
riscv/riscv-tests#263

Your obj

Need documentation for developers and contributors