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branch-prediction
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32-bit Superscalar RISC-V CPU
linux
asic
cpu
fpga
verilog
xilinx
superscalar
in-order
risc-v
branch-prediction
coremark
rv32i
verilator
riscv-linux
rv32im
artix-7
pipelined-processors
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Apr 18, 2020 - Verilog
cmake
cpu
pipeline
cpp
riscv
gtest
computer-architecture
speculation
branch-prediction
riscv32
riscv-simulator
riscv-emulator
tomasulo-algorithm
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Updated
Jul 2, 2020 - C++
Super scalar Processor design
processor-architecture
bison
flex
processor
assembler
parallel-computing
verilog
forwarding
bypassing
pipeline-processor
superscalar
opcode
verilog-hdl
instruction-set-architecture
instruction-set
processor-simulator
branch-prediction
pipeline-cpu
mnemonics
instruction-level-parallelism
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Sep 7, 2014 - Verilog
VHDL code of three branch predictors
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Jul 15, 2019 - VHDL
System benchmarks over JVM with JMH - SIMD (superscalar processing), Branch prediction, False sharing.
java
benchmarking
benchmark
jvm
transformations
simd
jmh
simd-parallelism
branch-prediction
jvm-metrics
jmh-benchmarks
java-benchmarks
simd-benchmark
simd-operation
java-memory-model
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Updated
Sep 11, 2018 - Java
A superscalar out-of‐order architectural simulator (With Memory Hierarchy).
java
processor
object-oriented
microprocessor
speculation
memory-hierarchy
processor-simulator
tomasulo
registers
branch-prediction
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Updated
Dec 10, 2016 - Java
Computer Architecture UIUC SP 2018
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May 4, 2018 - Assembly
A pipelined implementation of a MIPS processor that was optimized to use data forwarding, caching and branch prediction.
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Apr 20, 2017 - VHDL
Implementation of 4 different branch predictors in C
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May 21, 2020 - C
C++ Macro definitions for easy branch hinting.
library
cmake
cpp
makefile
gcc
macros
clang
icc
doxygen
make
cross
msvc
cpp-library
branch-prediction
branch-predictor
doxygen-documentation
static-branch-prediction
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Nov 6, 2018 - C++
Computer architecture related projects
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Nov 17, 2017 - C++
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Mar 27, 2020 - JavaScript
2 bit saturated branch predictor with BHR (Branch History Register)
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Dec 20, 2019 - C++
Some tests on SSE and branch prediction
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Nov 26, 2017 - C++
Branch Prediction Experiments
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Dec 6, 2019 - C++
Contains source code to carry out tests & analyse the results of various branch predictors against each other. Additionally, demonstrates the benefits of cache-oblivious algorithms. Done as part of VL-803 Processor Architecture course at IIIT-B (Spring 2020).
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May 9, 2020 - Shell
A MIPS processor with Cache and Advanced Branch Predictor written in SystemVerilog
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Jun 7, 2020 - SystemVerilog
ChampSim repository. Add-ons include the two-level-adaptive branch predictor by Yeh & Patt.
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Apr 1, 2020 - C++
Two Level Branch Predictor Simulator - EE382N Superscalar Microprocessor Architecture, Spring 2019, Assignment 4
simulator
computer-engineering
computer-architecture
superscalar
branch-prediction
branch-predictor
computer-engineering-lab
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Updated
May 19, 2020 - C++
A simple Java application to calculate hypothetical performance improvements of a tournament style branch prediction algorithm
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Mar 23, 2018 - Java
A Colaborative project on Branch Prediction using Deep Learning to make processors run conditional statements fast
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Jun 23, 2018 - Python
Correlating branch prediction simulator
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Mar 5, 2020 - Python
Hashed perceptron branch predictor simulator on Python3
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Apr 25, 2020 - Python
Branch Predictor is a C# program that runs a gshare branch prediction simulation, according to a specified number of Global Buffer Table (GBT) and Global History Record (GHR) bits. 2019.
branch-prediction
branch-predictor
gbt
ghr
global-branch-predictor
global-buffer-table
globar-history-record
gshare
gshare-table
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Jun 4, 2020 - C#
A language which abuses and misuses branch prediction [BSD license]
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Aug 18, 2014 - Scheme
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Some RISC-V instructions perform writes to 2 destinations, either 2 register or register or program counter. In cases if the source of one sub-operation matches a destination of another one, the order of result output is important. The examples are
jalrand instruction operating with CSRs:riscv/riscv-tests#258
riscv/riscv-tests#263
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