processor-architecture
Here are 70 public repositories matching this topic...
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May 23, 2020 - C++
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May 25, 2020 - C
For instance, if a user tries to write jalr x0 0(x1) the tooltip should also state that jalr has the format
jalr [rd] [rs] [imm].
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May 5, 2020 - Rust
We should probably have a general cleanup of configureLink when links are not allowed to be nullptr. This causes errors to be seg faults, instead of simple errors messages like "you forgot to add the expected link X"
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May 20, 2020 - PHP
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Jun 25, 2019 - C++
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Sep 7, 2014 - Verilog
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Apr 8, 2018 - Verilog
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Jul 13, 2019 - VHDL
Describe the bug
Command and instruction are used interchangeably in the taint code but they are two different things.
To Reproduce
N/A
Expected behavior
Sunflower commands should be referred to as commands and RISC-V instructions should be referred to as instructions. Someone should go through and ensure that command only refers to sunflower commands and instruction only refe
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May 18, 2020 - Java
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Feb 23, 2020 - VHDL
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Nov 21, 2019 - Coq
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Aug 20, 2018 - Verilog
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Sep 15, 2018
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May 14, 2017 - Assembly
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Jan 31, 2020 - Java
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Mar 7, 2019 - VHDL
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Oct 11, 2017
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Oct 7, 2016
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Mar 26, 2019 - Verilog
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Feb 7, 2016 - Limbo
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Jan 28, 2019 - Verilog
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Jun 27, 2019 - SystemVerilog
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Jul 20, 2017 - JavaScript
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Apr 22, 2017 - C++
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Collect coverage information at end of tests.
https://www.veripool.org/projects/verilator/wiki/Manual-verilator