Experimental validation of an analog spiking neural network with STDP learning rule in CMOS technology

TY - GEN

T1 - Experimental validation of an analog spiking neural network with STDP learning rule in CMOS technology

AU - Polidori, Elisabetta

AU - Camisa, Giovanni

AU - Mesri, Alireza

AU - Ferrari, Giorgio

AU - Polidori, Cristina

AU - Mastella, Michele

AU - Prati, Enrico

PY - 2022/10/28

Y1 - 2022/10/28

N2 - We report the design in CMOS technology and the experimental characterization of an analog spiking neural network with on-chip unsupervised learning. Long-term synaptic memory is implemented using a floating-gate device in a standard 150 nm CMOS process. The neurons are operated with a voltage supply of only 0.4V, allowing an extremely low power dissipation with an energy dissipation per synaptic operation of about 55 fJ. The CMOS chip includes the circuits for implementing real-time learning of the network based on the Spike Time Dependent Plasticity algorithm. During the learning, the neurons produce pulses of ±4.5 V that change the synaptic weight by activating tunneling currents to change the charge in the floating gates.

AB - We report the design in CMOS technology and the experimental characterization of an analog spiking neural network with on-chip unsupervised learning. Long-term synaptic memory is implemented using a floating-gate device in a standard 150 nm CMOS process. The neurons are operated with a voltage supply of only 0.4V, allowing an extremely low power dissipation with an energy dissipation per synaptic operation of about 55 fJ. The CMOS chip includes the circuits for implementing real-time learning of the network based on the Spike Time Dependent Plasticity algorithm. During the learning, the neurons produce pulses of ±4.5 V that change the synaptic weight by activating tunneling currents to change the charge in the floating gates.

KW - Nonvolatile memory

KW - Neurons

KW - Voltage

KW - Tunneling

KW - Analog circuits

KW - CMOS process

KW - Transistors

UR - https://ieeexplore.ieee.org/document/9967583/

U2 - 10.1109/MetroXRAINE54828.2022.9967583

DO - 10.1109/MetroXRAINE54828.2022.9967583

M3 - Conference contribution

SN - 978-1-6654-8575-3

SP - 187

EP - 192

BT - 2022 IEEE International Conference on Metrology for Extended Reality, Artificial Intelligence and Neural Engineering (MetroXRAINE)

PB - IEEE

T2 - 2022 IEEE International Conference on Metrology for Extended Reality, Artificial Intelligence and Neural Engineering (MetroXRAINE)

Y2 - 26 October 2022 through 28 October 2022

ER -