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    Stefan, in this en.wikipedia.org/wiki/Non-uniform_memory_access#/media/… (courtesy Wikipedia link you referred in your post) - Are there 2 NUMA nodes on each socket? As I understood, in this configuration, RAM is 32 GB and each Socket has 2 NUMA nodes, with each node being shared by 1 CPU Packages consisting of 8 processors, logical or otherwise. Am I correct? In my system, as you also mentioned, there is one NUMA node per socket (NUMA node0 CPU(s): 0-13,28-41). So, I suppose this pic is not an abstraction of the architecture of my system.?? Commented Sep 13, 2018 at 15:41
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    That image shows the NUMA architecture of a Bulldozer CPU; your Xeon CPU has a different architecture. NUMA layouts depend on the memory controllers, not the sockets (directly); you can have one memory controller per socket (as on current Xeon), multiple memory controllers per socket, or even external memory controller(s) instead. Commented Sep 13, 2018 at 15:45
  • Very helpful answer, but sometimes there are "On-line CPU(s) list" and "Off-line CPU(s) list", I assume “Thread(s) per core” × “Core(s) per socket” × “Socket(s)”. equals to the number of On-line CPU(s) list, not CPU(s) line? Commented Jan 26, 2024 at 2:26
  • @wjrforcyber “Thread(s) per core” × “Core(s) per socket” × “Socket(s)” describes the available hardware, and matches the “CPU(s)” line. Commented Jan 26, 2024 at 13:13