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    To clarify: The 6502 was microprogrammed, so do microprogrammed CPUs that fetch the instruction register in parallel with doing other work count? I guess there'd be quite a few of those earlier than the 6502. Also, keep in mind that if we are talking 6502 or earlier, memory is usually faster than the CPU, so if you want parallelism, you want that on the CPU. Commented Jan 18, 2021 at 10:00
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    @dirkt: I wouldn't really call the 6502 microprogrammed. It does use a PLA internally, but the term "microprogrammed" usually refers to CPUs whose microcode can branch and loop; the 6502, by contrast, advances through states purely in sequence except when it skips to the start of the next instruction, or when it the main sequencer is stalled either because the "ready" signal is low or the CPU is performing a read-modify-write sequence (which is controlled via a different latch). Commented Jan 18, 2021 at 17:41
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    Why only "microprocessors"? For this I think we have to go back to at least the CDC 6600. Commented Jan 18, 2021 at 23:43
  • If one excludes delayed loads such as used by MIPS R2000 (where the load operation has a fixed delay during which another independent operation could execute), this ability is called "non-blocking loads". In-order designs which use a scoreboard to determine operation readiness could support such (and load operations are one of the common multicycle and variable latency operations). Commented Feb 19, 2021 at 16:19