🚀 Prospective Silicon Architect
I am interested in cross-layer AI workload optimization, from model level to microarchitecture level.
- M.S. Electrical Engineering (SoC subgroup) @ NSYSU, Taiwan (System Co-Design Lab)
- ongoing research: memory-centric accelerator architecture targeting 3D-UNet workload (🔎 current focus)
- tools: Gem5, Timeloop/Accelergy, Verilator, HBM-enabled FPGA (Xilinx Alveo U55c)
- keywords: domain specific architecture (DSA), performance modeling, FPGA prototyping, HBM
- B.S. Computer Science (AI subgroup) @ NCCU, Taiwan
- research focus: AI model architecture optimization, AI edge applications
- An Improved Spatial Transformer Network based on Lightweight Localization Net (L-STN) (ISASD 2024)
- Real-Time Video-Based Measurement of Back Angles Using YOLOv8 and Edge Detection for Strength Training (IJETI 2026)
- Hardware–Software Co-Design: cross-layer optimization, from workload to microarchitecture
- Performance Modeling & Memory Systems: design space exploration (DSE), memory-centric architecture
- FPGA-Based Prototyping: real architecture improvement claims require silicon-proven backup
| Course | Description | Skills |
|---|---|---|
| Open Source Prototype Systems | RISC-V pipelined CPU implementation with memory subsystem | RISC-V toolchain |
| Computer Architecture | model and evaluate workloads across processors and configurations on Gem5 | RISC-V, Gem5 simulator |
| SOPC System Design | AXI-based FPGA system integrating custom accelerators on Zedboard | AMBA AXI, AI acceleration, Vivado SDK, Linux driver |
| DLab | FPGA hands-on implementation | Verilog, Vivado |
- Publish first paper — 3D-UNet Performance Modeling and HBM-based Memory-Centric Architecture
- End-to-end FPGA prototyping on Alveo U55C
- From FPGA prototypes to tapeout-ready IC design