Abstract
The quiescent current (I DDQ) consumed by a CMOS IC is a good indicator of the presence of a large class of defects. However, the effectiveness of I DDQ testing requires appropriate discriminability of defective and defect-free currents, and hence it becomes necessary to estimate the currents involved in order to design the I DDQ test. In this work, we present a method to estimate accurately the non-defective I DDQ consumption based on a hierarchical approach at electrical (cell) and logic (circuit) levels. This accurate estimator is used in conjunction with an ATPG (Automatic Test Pattern Generation) to obtain vectors having low/high defect-free I DDQ currents.
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Ferré, A., Figueras, J. LEAP: An Accurate Defect-Free IDDQ Estimator. Journal of Electronic Testing 17, 267–274 (2001). https://doi.org/10.1023/A:1012215412601
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DOI: https://doi.org/10.1023/A:1012215412601