default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDSoC 2008: Tampere, Finland
- 2008 IEEE International Symposium on System-on-Chip, SOC 2008, Tampere, Finland, November 5-6, 2008. IEEE 2008, ISBN 978-1-4244-2541-9
- Hamed Aminzadeh
, Reza Lotfi, Khalil Mafinezhad:
Area-efficient low-cost low-dropout regulators using MOS capacitors. 1-4 - Kurt Schweiger, Horst Zimmermann:
A 65nm CMOS down-sampling micromixer with enhanced DC current capability. 1-4 - Heimo Uhrmann, Horst Zimmermann:
A 1V current-mode filter in 65nm CMOS using capacitance multiplication. 1-4 - Luca Henzen, Flavio Carbognani, Norbert Felber, Wolfgang Fichtner:
FPGA implementation of a 2G fibre channel link encryptor with authenticated encryption mode GCM. 1-4 - Erno Salminen, Ari Kulmala, Timo Hämäläinen:
On the credibility of load-latency measurement of network-on-chips. 1-7 - Ganesh Garga, Mythri Alle, Keshavan Varadarajan, S. K. Nandy, H. S. Jamadagni:
Realizing a flexible constraint length Viterbi decoder for software radio on a de Bruijn interconnection network. 1-4 - Sami Boukhechem, El-Bay Bourennane:
TLMCO-simulation for an open source MPSOC platform under STARSoC environment. 1-6 - Camille Jalier, Didier Lattard, Gilles Sassatelli:
A flexible modeling and simulation framework for Design Space Exploration. 1-4 - H. Kooti, Mohammad Mirza-Aghatabar, Shaahin Hessabi, Arash Tavakkol:
Energy analysis of re-injection based deadlock recovery routing algorithms. 1-4 - Fateh Boutekkouk, Sébastien Bilavarn, Michel Auguin, Mohammed Benmohammed:
UML profile for estimating application Worst Case Execution Time on System-on-Chip. 1-6 - Heikki Hurskainen, Jussi Raasakka, Jari Nurmi:
Specification of GNSS application for multiprocessor platform. 1-6 - Mojtaba Valinataj, Siamak Mohammadi, Saeed Safari:
Inherent reliability evaluation of Networks-on-Chip based on analytical models. 1-4 - Fabio Garzia, Claudio Brunelli, Carmelo Giliberto, Roberto Airoldi, Jari Nurmi:
Implementation of W-CDMA slot synchronization on a reconfigurable System-on-Chip. 1-4 - Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf:
FlexPath NP - A network processor architecture with flexible processing paths. 1-6 - Heikki Kariniemi, Jari Nurmi:
Micronmesh for fault-tolerant GALS Multiprocessors on FPGA. 1-8 - Karri Nikunen, Hannu Heusala, Jeppe Komulainen:
Configuring Smart Objects over cognitive radio. 1-4 - Kalle Holma, Tero Arpinen, Erno Salminen, Marko Hännikäinen, Timo Hämäläinen:
Real-time execution monitoring on multi-processor system-on-chip. 1-6 - Manuel Ortiz, María Brox, Francisco Javier Quiles-Latorre, Andrés Gersnoviez, Carlos Diego Moreno-Moreno, M. Montijano:
Using soft processors for component design in SOC: A case-study of timers. 1-4 - Yosi Ben-Asher, Nadav Rotem:
Synthesis for variable pipelined function units. 1-4 - Peng Wang, Hannu Tenhunen, Dian Zhou, Lirong Zheng:
PER performance enhancement through antenna and transceiver co-design for multi-band OFDM UWB communication. 1-5 - Vladimír Guzma, Shuvra S. Bhattacharyya, Pertti Kellomäki, Jarmo Takala:
Trade-offs in mapping high-level dataflow graphs onto ASIPs. 1-4 - Ning Ma, Zhibo Pang, Hannu Tenhunen, Lirong Zheng:
An ASIC-design-based configurable SOC architecture for networked media. 1-4 - Ewerson Carvalho, Fernando Moraes:
Congestion-aware task mapping in heterogeneous MPSoCs. 1-4 - Stergios Stergiou, Jawahar Jain:
Optimizing routing tables on systems-on-chip with Content-Addressable Memories. 1-6 - Maoxiang Yi, Huaguo Liang, Zhengfeng Huang:
Balancing wrapper chains of SoC core based on best interchange decreasing. 1-4 - Muhammad E. S. Elrabaa:
A two-phase return-to-zero (RZ) asynchronous transceiver circuit for pipe-lined SoC interconnects. 1-4 - Nikolaos Minas, David Kinniment, Gordon Russell, Alex Yakovlev:
High resolution flash time-to-digital converter with sub-picosecond measurement capabilities. 1-4 - Liang Rong, Fredrik Jonsson, Lirong Zheng, Mats Carlsson, Charlotta Hedenas:
RF transmitter architecture investigation for power efficient mobile WiMAX applications. 1-4 - Heikki Orsila, Erno Salminen, Marko Hännikäinen, Timo Hämäläinen:
Evaluation of heterogeneous multiprocessor architectures by energy and performance optimization. 1-6 - Stavros Georgiopoulos, Grigoris Dimitroulakos, Costas E. Goutis:
Integrating high speed multipliers in Coarse Grain Reconfigurable Arrays. 1-4 - Heikki Berg, Claudio Brunelli, Ulf Lücking:
Analyzing models of computation for software defined radio applications. 1-4 - Mohammad Arjomand, Hamid Sarbazi-Azad, S. Hamid Amiri:
Multi-Objective Genetic optimized multiprocessor SoC design. 1-4 - Taeyoon Kim, Wonki Park, Heesun Ahn, Kyongwon Min, Sangyong Lee, Jongchan Choi, Chulwoo Kim, Kynnyun Kim, Sungchul Lee:
A 110 dB, 3-mW fourth-order Σ-Δ modulator for atmospheric pressure sensor. 1-4 - Ali Ahmadinia, Balal Ahmad, Tughrul Arslan:
A state based framework for efficient system-level power estimation of of costum reconfigurable cores. 1-4 - Peng Wang, Fredrik Jonsson, Dian Zhou, Lirong Zheng:
Low noise amplifier architecture analysis for UWB system. 1-4 - Aleksandar Milutinovic, Kees Goossens, Gerard J. M. Smit:
Impact of power-management granularity on the energy-quality trade-off for soft and hard real-time applications. 1-4
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-07-28 23:26 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated, funded, and maintained by:
Schloss Dagstuhl - Leibniz Center for Informatics is a member of the Leibniz Association and is funded by the federal government of Germany and the states of Germany, especially Saarland and Rhineland‑Palatinate.
