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ORCID36th DFT 2021: Athens, Greece
- Luigi Dilillo, Luca Cassano, Athanasios Papadimitriou:
36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021, Athens, Greece, October 6-8, 2021. IEEE 2021, ISBN 978-1-6654-1609-2 - Puneet Ramesh Savanur, Spyros Tragoudas:
A Fault Model to Detect Design Errors in Combinational Circuits. 1-4 - Zahra Kazemi, Amin Norollah, Afef Kchaou, Mahdi Fazeli, David Hély, Vincent Beroulle:
An In-Depth Vulnerability Analysis of RISC-V Micro-Architecture Against Fault Injection Attack. 1-6 - Davide Bellizia, Nadia El Mrabet, Apostolos P. Fournaris, Simon Pontié, Francesco Regazzoni
, François-Xavier Standaert, Élise Tasso, Emanuele Valea:
Post-Quantum Cryptography: Challenges and Opportunities for Robust and Secure HW Design. 1-6 - Sébastien Thomet, Serge De Paoli, Jean-Marc Daveau, Valérie Bertin, Fady Abouzeid, Philippe Roche, Fakhreddine Ghaffari, Olivier Romain:
FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a Chip. 1-6 - Wei Chang, Yu-Guang Chen, Po-Yeh Huang, Jin-Fu Li:
An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing. 1-4 - Vijay K. Jain, Glenn H. Chapman:
Fault Tolerance for Islandable-Microgrid Sensors. 1-4 - Marko S. Andjelkovic, Oliver Schrape, Anselm Breitenreiter, Junchao Chen, Milos Krstic:
A Tunable Single Event Transient Filter Based on Digitally Controlled Capacitive Delay Cells. 1-6 - Hideyuki Ichihara, Takayuki Fukuda, Tomoo Inoue:
A Design of Reliable Linear FSMs with Equivalent States in Stochastic Computing. 1-6 - Irith Pomeranz:
Zoom-In Feature for Storage-Based Logic Built-In Self-Test. 1-6 - Pelopidas Tsoumanis, Georgios Ioannis Paliaroutis, Nestoras E. Evmorfopoulos, George I. Stamoulis:
On the Impact of Electrical Masking and Timing Analysis on Soft Error Rate Estimation in Deep Submicron Technologies. 1-6 - Md Toufiq Hasan Anik, Jean-Luc Danger, Omar Diankha, Mohammad Ebrahimabadi, Christoph Frisch, Sylvain Guilley, Naghmeh Karimi, Michael Pehl, Sofiane Takarabt:
Testing and Reliability Enhancement of Security Primitives. 1-8 - Hardi Selg, Maksim Jenihhin, Peeter Ellervee:
JÄNES: A NAS Framework for ML-based EDA Applications. 1-6 - Anuraag Narang, Balaji Venn, S. Saqib Khursheed, Peter Harrod:
An Exploration of Microprocessor Self-Test Optimisation Based On Safe Faults. 1-6 - Dake Chen, Chunxiao Lin, Peter A. Beerel:
GF-Flush: A GF(2) Algebraic Attack on Dynamically Secured Scan Chains. 1-6 - Stavros Simoglou, Christos P. Sotiriou, Nikolaos Blias:
Static Timing Analysis Induced Simulation Errors for Asynchronous Circuits. 1-4 - Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Mauro Olivieri:
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design. 1-4 - Marcel Merten, Sebastian Huhn, Rolf Drechsler:
A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks. 1-6 - L. Degli Abbati, Rudolf Ullmann, G. Paganini, Matteo Coppetta, L. Zaia, Vincent Huard, Olivier Montfort, Riccardo Cantoro, Giorgio Insinga, F. Venini, P. Calao, Paolo Bernardi:
Industrial best practice: cases of study by automotive chip- makers. 1-6 - Cristiana Bolchini, Luca Cassano, Andrea Mazzeo, Antonio Miele:
Usability-based Cross-Layer Reliability Evaluation of Image Processing Applications. 1-6 - Sandeep Kumar, Atin Mukherjee:
A Self-Healing, High Performance and Low-Cost Radiation Hardened Latch Design. 1-6 - Vishal Gupta, Giulio Panunzi, Saurabh Khandelwal, Eugenio Martinelli, Abusaleh M. Jabir, Marco Ottavi:
Reliability Assessment of Memristor based Gas Sensor Array. 1-6 - Romain Mercier, Cédric Killian, Angeliki Kritikakou, Youri Helen, Daniel Chillet:
A Region-Based Bit-Shuffling Approach Trading Hardware Cost and Fault Mitigation Efficiency. 1-4 - Alessandro Palumbo, Luca Cassano, Pedro Reviriego, Giuseppe Bianchi, Marco Ottavi:
A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses. 1-6 - Glenn H. Chapman, Simone Neufeld, Klinsmann J. Coelho Silva Meneses, Israel Koren, Zahava Koren:
Dependence of SEUs in Digital Cameras on Pixel size and Elevation. 1-4 - Elaheh Malekzadeh, Nezam Rohbani, Zhonghai Lu, Masoumeh Ebrahimi:
The Impact of Faults on DNNs: A Case Study. 1-6 - Panayiotis Corneliou, Panagiota Nikolaou, Maria K. Michael, Theocharis Theocharides:
Fine-Grained Vulnerability Analysis of Resource Constrained Neural Inference Accelerators. 1-6 - Corrado De Sio, Sarah Azimi, Andrea Portaluri, Luca Sterpone:
SEU Evaluation of Hardened-by-Replication Software in RISC- V Soft Processor. 1-6 - Aneesh Balakrishnan, Guilherme Cardoso Medeiros, Cemil Cem Gürsoy, Said Hamdioui, Maksim Jenihhin, Dan Alexandrescu:
Modeling Soft-Error Reliability Under Variability. 1-6 - Nabanita Ghoshal, Sree Rama K. C. Saraswatula, Santosh Yachareni, Shidong Zhou, Anil Kumar Kandala, Narendra Kumar Pulipati:
Mitigation of the impact of across chip systematic process variation using a novel system level design. 1-4 - Mohamed Amine Khelif, Jordane Lorandel, Olivier Romain:
Non-invasive I2C Hardware Trojan Attack Vector. 1-6 - Stéphane Burel, Adrian Evans, Lorena Anghel:
Zero-Overhead Protection for CNN Weights. 1-6 - Zhen Gao, Ruize Wang, Haoyu Du, Pedro Reviriego:
Analysis and Evaluation of the Effects of Single Event Upsets (SEU s) on Memories in Polar Decoders. 1-6 - Endri Kaja, Nicolas Gerlin, Mounika Vaddeboina, Luis Rivas, Sebastian Siegfried Prebeck, Zhao Han, Keerthikumara Devarajegowda, Wolfgang Ecker:
Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models. 1-6 - Christos Georgakidis, Iordanis Lilitsis, Georgios Stanimeropoulos, Christos P. Sotiriou:
RADPlace: A Timing-aware RAdiation-Hardening Detailed Placement Scheme Satisfying TMR Spacing Constraints. 1-6 - Zhen Gao, Jiajun Xiao, Pedro Reviriego:
Reliability Evaluation of Digital Channelizers Implemented on SRAM - FPGAs. 1-4 - Ioanna Souvatzoglou, Athanasios Papadimitriou, Aitzan Sari, Vasileios Vlagkoulis, Mihalis Psarakis:
Analyzing the Single Event Upset Vulnerability of Binarized Neural Networks on SRAM FPGAs. 1-6
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